Entity: adc32rf45

Diagram

time TPD_G real CLK_PERIOD_G real SPI_SCLK_PERIOD_G sl axiClk sl axiRst AxiLiteReadMasterType axiReadMaster AxiLiteWriteMasterType axiWriteMaster sl coreSDin AxiLiteReadSlaveType axiReadSlave AxiLiteWriteSlaveType axiWriteSlave sl coreRst sl coreSclk sl coreSDout sl coreCsb

Description

Company : SLAC National Accelerator Laboratory

Description: SPI Master Wrapper that includes a state machine for SPI paging

This file is part of 'SLAC Firmware Standard Library'. It is subject to the license terms in the LICENSE.txt file found in the top-level directory of this distribution and at: https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. No part of 'SLAC Firmware Standard Library', including this file, may be copied, modified, propagated, or distributed except according to

the terms contained in the LICENSE.txt file.

Generics

Generic name Type Value Description
TPD_G time 1 ns
CLK_PERIOD_G real (1.0/156.25E+6)
SPI_SCLK_PERIOD_G real (1.0/10.0E+6)

Ports

Port name Direction Type Description
axiClk in sl Clock and Reset
axiRst in sl
axiReadMaster in AxiLiteReadMasterType AXI-Lite Interface
axiReadSlave out AxiLiteReadSlaveType
axiWriteMaster in AxiLiteWriteMasterType
axiWriteSlave out AxiLiteWriteSlaveType
coreRst out sl SPI Interface
coreSclk out sl
coreSDin in sl
coreSDout out sl
coreCsb out sl

Signals

Name Type Description
r RegType
rin RegType
rdEn sl
rdData slv(23 downto 0)

Constants

Name Type Value Description
DLY_C natural integer(1.0E-6/CLK_PERIOD_G) min. 1us delay between SPI cycles
REG_INIT_C RegType ( rst => '0',
axiRd => '0',
wrEn => '0',
wrData => (others => '0'),
data => (others => '0'),
addr => (others => '0'),
xferType => (others => '0'),
timer => 0,
cnt => 0,
size => 0,
wrArray => (others => (others => '0')),
axiWriteSlave => AXI_LITE_WRITE_SLAVE_INIT_C,
axiReadSlave => AXI_LITE_READ_SLAVE_INIT_C,
state => IDLE_S)

Types

Name Type Description
StateType ( IDLE_S,
INIT_S,
REQ_S,
ACK_S)
RegType

Processes

Instantiations