Package: arch_package

Description

MICRON TECHNOLOGY, INC. - CONFIDENTIAL AND PROPRIETARY INFORMATION

Signals

Name Type Description
cmd UTYPE_cmdtype
raw_cmd UTYPE_cmdtype
rank int
bank_group int
bank int
addr int
odt bit Defaults to 0.
sim_time int Population optional.
cycle_count int Population optional.
tCK int
typedef endclass
UTYPE_blreg enum {
rBL8=0,
rBLFLY=1,
rBL4=2}
_debug bit
_by_mode int
_num_dms int
endpackage endclass

Constants

Name Type Value Description
MAX_DM_BITS int 2
MAX_DBI_BITS int MAX_DM_BITS DM/DBI share pins in current spec.
MAX_ADDR_BITS int 21
MAX_ROW_ADDR_BITS int 18
MAX_COL_ADDR_BITS int 13 Include AP/BLFLY
MAX_BANK_BITS int 2
MAX_RANK_BITS int 3
MAX_DQ_BITS int 16
MAX_DQS_BITS int 2
MAX_CRC_EQUATION int 8
MAX_CRC_TRANSFERS int 2
MAX_BANK_GROUP_BITS int 2
MAX_BURST_LEN int 8
AUTOPRECHARGEADDR int 10
BLFLYSELECT int 12
BANK_GROUP_SHIFT int MAX_ADDR_BITS + MAX_BANK_BITS
BANK_SHIFT int MAX_ADDR_BITS
MAX_MODEREGS int 2
MODEREG_BITS int MAX_ADDR_BITS + MAX_BANK_BITS + MAX_BANK_GROUP_BITS
MAX_MODEREG_SET_BITS int 14
MAX_BANKS_PER_GROUP int 2
MAX_BANK_GROUPS int 2
MAX_RANKS int 2
RTT_BITS int 16
FAW_DEPTH int 4
LOAD_MODE_CMD 5'b01000 {cs, act, ras, cas, we}
MIN_BL int 4
DEF_BL int 8
MAX_BL int MAX_BURST_LEN
DEF_BT UTYPE_bt INT
MIN_CL int 5
MAX_CL int 32
DEF_CL int 12
MIN_AL int 0
MAX_AL_REG int 2
MAX_AL_CLKS int MAX_CL - 1
MIN_CWL int 9
MAX_CWL int 20
DEF_CWL int 12
MIN_RL int MIN_CL - 1 subtract one for the DLL disable mode.
MAX_RL int MAX_CL + MAX_AL_CLKS
MIN_WL int 5
MAX_WL int MAX_CWL + MAX_AL_CLKS
MIN_WR int 10
MAX_WR int 28
DEF_WR int 12
MAX_CAL int 8
DEF_CAL int 0
DEF_LPASR UTYPE_lpasr LPASR_NORM
DEF_RTTW UTYPE_rttw RTTW_DIS
DEF_MPR_MODE UTYPE_mpr SERIAL
DEF_DELAY_WRITE UTYPE_delay_write_crc_dm DELAY_WRITE_4
MPR_DATA_BITS int 8
MPR_SELECT_BITS int 2
MAX_MPR_PATTERNS int 2
MPR_TEMP_BITS int 2
MAX_MPR_TEMPS int 2
MPR_TEMP0 int 'b0000_0000
MPR_TEMP1 int 'b0000_0001
MPR_TEMP2 int 'b0000_0010
MPR_TEMP3 int 'b0000_0011
MAX_MPR_DEFAULT_PATTERNS int 4
MPR_PAT_DEFAULT0 int 'b0101_0101
MPR_PAT_DEFAULT1 int 'b0011_0011
MPR_PAT_DEFAULT2 int 'b0000_1111
MPR_PAT_DEFAULT3 int 'b0000_0000
MODE_REG_WIDTH int MODEREG_BITS Mode Register Definitions
MODEREG_BITS reg[MODEREG_BITS:0] '0
MODEREG_BITS reg[MODEREG_BITS:0] MR0 2'b00 << BANK_GROUP_SHIFT
MODEREG_BITS reg[MODEREG_BITS:0] MR0 2'b00 << BANK_GROUP_SHIFT
MODEREG_BITS reg[MODEREG_BITS:0] MR0 2'b00 << BANK_GROUP_SHIFT
MODEREG_BITS reg[MODEREG_BITS:0] MR0 2'b01 << BANK_GROUP_SHIFT
MODEREG_BITS reg[MODEREG_BITS:0] MR0 2'b01 << BANK_GROUP_SHIFT
MODEREG_BITS reg[MODEREG_BITS:0] MR0 2'b01 << BANK_GROUP_SHIFT
MODEREG_BITS reg[MODEREG_BITS:0] MR0 2'b01 << BANK_GROUP_SHIFT
MODEREG_BITS reg[MODEREG_BITS:0] 'b0011_1100_0000_1000_0000 MR0 Codes
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_0000_0000
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_0000_0001
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_0000_0010
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_0000_0011
MODEREG_BITS reg[MODEREG_BITS:0] MR0_BLFLY
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_0000_0011
NUM_BLMODE int 4
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_0000_0000
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_0000_1000
MODEREG_BITS reg[MODEREG_BITS:0] MR0_SEQ
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_0000_1000
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_0000_0000
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_0000_0100
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_0001_0000
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_0001_0100
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_0010_0000
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_0010_0100
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_0011_0000
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_0011_0100
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_0100_0000
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_0100_0100
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_0101_0000
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_0101_0100
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_0110_0000
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_0110_0100
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_0111_0000
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_0111_0100
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0001_0000_0000_0000
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0001_0000_0000_0100
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0001_0000_0001_0000
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0001_0000_0001_0100
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0001_0000_0010_0000
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0001_0000_0010_0100
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0001_0000_0011_0000
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0001_0000_0011_0100
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0001_0000_0111_0100
MODEREG_BITS reg[MODEREG_BITS:0] MR0_CL12
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0001_0000_0000
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_0000_0000
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0010_0000_0000
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0100_0000_0000
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0110_0000_0000
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_1000_0000_0000
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_1010_0000_0000
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_1100_0000_0000
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_1110_0000_0000
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0010_0000_0000_0000
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0010_0010_0000_0000
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0010_0100_0000_0000
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0010_0110_0000_0000
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0010_1000_0000_0000
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0010_1010_0000_0000
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0010_1100_0000_0000
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0010_1110_0000_0000
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0010_1110_0000_0000
MODEREG_BITS reg[MODEREG_BITS:0] MR0_WR12
MODEREG_BITS reg[MODEREG_BITS:0] 'b0011_1110_0000_0110_0000 `MR1
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_0000_0000 `MR1
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_0000_0001 `MR1
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_0000_0001 `MR1
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_0000_0000 `MR1
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_0000_0010 `MR1
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_0000_0100 `MR1
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_0000_0110 `MR1
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_0000_0110 `MR1
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_0000_0000 `MR1
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_0000_1000 `MR1
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_0001_0000 `MR1
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_0001_1000 `MR1
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_0001_1000 `MR1
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_0001_1000 `MR1
MODEREG_BITS reg[MODEREG_BITS:0] MR1_AL0
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_0000_0000 `MR1
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_1000_0000 `MR1
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_1000_0000 `MR1
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_0000_0000 `MR1
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0001_0000_0000 `MR1
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0010_0000_0000 `MR1
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0011_0000_0000 `MR1
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0100_0000_0000 `MR1
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0101_0000_0000 `MR1
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0110_0000_0000 `MR1
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0111_0000_0000 `MR1
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0111_0000_0000 `MR1
MODEREG_BITS reg[MODEREG_BITS:0] MR1_RTTN_DIS
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_0000_0000 `MR1
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_1000_0000_0000 `MR1
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_1000_0000_0000 `MR1
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_0000_0000 `MR1
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0001_0000_0000_0000 `MR1
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0001_0000_0000_0000 `MR1
MODEREG_BITS reg[MODEREG_BITS:0] 'b0011_1100_0000_0000_0000 `MR2
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_0000_0000 `MR2
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_0000_0001 `MR2
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_0000_0010 `MR2
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_0000_0011 `MR2
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_0000_0011 `MR2
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_0000_0000 `MR2
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_0000_0100 `MR2
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0001_0000_0000 `MR2
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0001_0000_0100 `MR2
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0001_0000_0100 `MR2
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_0000_0000 `MR2
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_0000_1000 `MR2
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_0001_0000 `MR2
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_0001_1000 `MR2
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_0010_0000 `MR2
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_0010_1000 `MR2
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_0011_0000 `MR2
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_0011_1000 `MR2
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_0011_1000 `MR2
MODEREG_BITS reg[MODEREG_BITS:0] MR2_CWL12
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_0000_0000 `MR2
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_0100_0000 `MR2
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_1000_0000 `MR2
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_1100_0000 `MR2
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_1100_0000 `MR2
MODEREG_BITS reg[MODEREG_BITS:0] MR2_LPASR_NORM
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_0000_0000 `MR2
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0010_0000_0000 `MR2
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0100_0000_0000 `MR2
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0110_0000_0000 `MR2
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_1000_0000_0000 `MR2
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_1010_0000_0000 `MR2
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_1100_0000_0000 `MR2
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_1110_0000_0000 `MR2
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_1110_0000_0000 `MR2
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_0000_0000 `MR2
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0001_0000_0000_0000 `MR2
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0001_0000_0000_0000 `MR2
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_0000_0000 `MR2
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0010_0000_0000_0000 `MR2
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0010_0000_0000_0000 `MR2
MODEREG_BITS reg[MODEREG_BITS:0] 'b0011_1110_0000_0000_0000 `MR3
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_0000_0000 `MR3
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_0000_0001 `MR3
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_0000_0010 `MR3
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_0000_0011 `MR3
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_0000_0011 `MR3
MODEREG_BITS reg[MODEREG_BITS:0] MR3_MPR_PATTERN
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_0000_0000 `MR3
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_0000_0100 `MR3
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_0000_0100 `MR3
MODEREG_BITS reg[MODEREG_BITS:0] MR3_MPR_DIS
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_0000_0000 `MR3
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_0000_1000 `MR3
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_0000_1000 `MR3
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_0000_0000 `MR3
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_0001_0000 `MR3
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_0001_0000 `MR3
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_0000_0000 `MR3
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_0010_0000 `MR3
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_0010_0000 `MR3
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_0000_0000 `MR3
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_0100_0000 `MR3
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_1000_0000 `MR3
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_1100_0000 `MR3
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0001_0000_0000 `MR3
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0001_0100_0000 `MR3
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0001_1000_0000 `MR3
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0001_1100_0000 `MR3
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0001_1100_0000 `MR3
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_0000_0000 `MR3
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0010_0000_0000 `MR3
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0100_0000_0000 `MR3
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0110_0000_0000 `MR3
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0110_0000_0000 `MR3
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_0000_0000 `MR3
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_0000_0000 `MR3
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_1000_0000_0000 `MR3
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0001_0000_0000_0000 `MR3
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0001_1000_0000_0000 `MR3
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0001_1000_0000_0000 `MR3
MODEREG_BITS reg[MODEREG_BITS:0] MR3_MPR_SERIAL
MODEREG_BITS reg[MODEREG_BITS:0] 'b0011_1100_0000_0010_0000 `MR4
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_0000_0000 `MR4
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_0000_0010 `MR4
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_0000_0010 `MR4
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_0000_0000 `MR4
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_0000_0100 `MR4
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_0000_0100 `MR4
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_0000_0000 `MR4
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_0000_1000 `MR4
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_0000_1000 `MR4
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_0000_0000 `MR4
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_0001_0000 `MR4
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_0001_0000 `MR4
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_0000_0000 `MR4
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_0100_0000 `MR4
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_1000_0000 `MR4
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_1100_0000 `MR4
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0001_0000_0000 `MR4
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0001_0100_0000 `MR4
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0001_1000_0000 `MR4
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0001_1100_0000 `MR4
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0001_1100_0000 `MR4
MODEREG_BITS reg[MODEREG_BITS:0] MR4_CAL0
MR4_CAL_SHIFT int 6
MR4_CAL_BITS int 3
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_0000_0000 `MR4
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0010_0000_0000 `MR4
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0010_0000_0000 `MR4
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_0000_0000 `MR4
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0100_0000_0000 `MR4
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0100_0000_0000 `MR4
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_0000_0000 `MR4
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_1000_0000_0000 `MR4
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_1000_0000_0000 `MR4
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_0000_0000 `MR4
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0001_0000_0000_0000 `MR4
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0001_0000_0000_0000 `MR4
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_0000_0000 `MR4
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0010_0000_0000_0000 `MR4
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0010_0000_0000_0000 `MR4
MODEREG_BITS reg[MODEREG_BITS:0] 'b0011_1100_0000_0000_0000 `MR5
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_0000_0000 `MR5
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_0000_0001 `MR5
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_0000_0010 `MR5
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_0000_0011 `MR5
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_0000_0100 `MR5
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_0000_0101 `MR5
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_0000_0110 `MR5
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_0000_0111 `MR5
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_0000_0111 `MR5
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_0000_0000 `MR5
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_0000_1000 `MR5
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_0000_1000 `MR5
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_0000_0000 `MR5
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_0001_0000 `MR5
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_0001_0000 `MR5
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_0000_0000 `MR5
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_0010_0000 `MR5
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_0010_0000 `MR5
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_0000_0000 `MR5
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_0100_0000 `MR5
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_1000_0000 `MR5
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_1100_0000 `MR5
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0001_0000_0000 `MR5
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0001_0100_0000 `MR5
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0001_1000_0000 `MR5
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0001_1100_0000 `MR5
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0001_1100_0000 `MR5
MODEREG_BITS reg[MODEREG_BITS:0] MR5_RTTP_DIS
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_0000_0000 `MR5
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0010_0000_0000 `MR5
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0010_0000_0000 `MR5
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_0000_0000 `MR5
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0100_0000_0000 `MR5
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0100_0000_0000 `MR5
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_0000_0000 `MR5
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_1000_0000_0000 `MR5
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_1000_0000_0000 `MR5
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_0000_0000 `MR5
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0001_0000_0000_0000 `MR5
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0001_0000_0000_0000 `MR5
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_0000_0000 `MR5
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0010_0000_0000_0000 `MR5
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0010_0000_0000_0000 `MR5
MODEREG_BITS reg[MODEREG_BITS:0] 'b0011_1110_0000_0000_0000 `MR6
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_0011_1111 `MR6
MR6_VREF_OFFSET_SHIFT int 0
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_0000_0000 `MR6
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_0100_0000 `MR6
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_0100_0000 `MR6
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_0000_0000 `MR6
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_1000_0000 `MR6
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_1000_0000 `MR6
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0000_0000_0000 `MR6
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_0100_0000_0000 `MR6
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_1000_0000_0000 `MR6
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0000_1100_0000_0000 `MR6
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0001_0000_0000_0000 `MR6
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0001_0100_0000_0000 `MR6
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0001_1000_0000_0000 `MR6
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0001_1100_0000_0000 `MR6
MODEREG_BITS reg[MODEREG_BITS:0] 'b0000_0001_1100_0000_0000 `MR6
MODEREG_BITS reg[MODEREG_BITS:0] 'b0011_1111_1111_1111_1111 `MR7

Types

Name Type Description
UTYPE_TS enum {
TS_1875,
TS_1500,
TS_1250,
TS_1072,
TS_938,
TS_833,
TS_750,
TS_682,
TS_625,
NUM_TS }
UTYPE_tCKMode enum {
TCK_MIN,
TCK_MAX,
TCK_RANDOM }
UTYPE_TimingParameters struct packed {
UTYPE_TS ts_loaded;
UTYPE_tCKMode tck_mode;
int ClockDutyCycle,
tCHp_min,
tCHp_max;
int tCK,
tCK_min,
tCK_max,
tCK_shmoo,
tOffset;
int tDQSQ,
tQHp,
tDS,
tDH,
tIPW;
int tRPREp,
tRPSTp,
tQSHp,
tQSLp;
int tWPSTp,
tWPREp;
int tDQSCK,
tDQSCK_min,
tDQSCK_max,
tDQSCK_dll_on,
tDQSCK_dll_off,
tDQSCK_dll_off_min,
tDQSCK_dll_off_max;
int tDQSLp,
tDQSLp_min,
tDQSLp_max,
tDQSHp_min,
tDQSHp_max,
tDQSHp;
int tDQSSp,
tDQSSp_min,
tDQSSp_max,
tDQSSp_2tCK_min,
tDQSSp_2tCK_max,
tDQSSp_1tCK_min,
tDQSSp_1tCK_max;
int tDLLKc;
int tRTP,
tRTPc,
tRTP_min,
tRTPc_min;
int tWTR_L,
tWTRc_L,
tWTR_L_CRC_DM,
tWTRc_L_CRC_DM;
int tWTR_S,
tWTRc_S,
tWTR_S_CRC_DM,
tWTRc_S_CRC_DM;
int tWR,
tWRc,
tWR_CRC_DMc,
tWR_MPRc;
int tCAL_min,
tCALc_min;
int tMRDc,
tMOD,
tMODc,
tMPRRc;
int tRCD,
tRCDc,
tRP,
tRPc,
tRAS,
tRASc,
tRC,
tRCc;
int tCCD_L,
tCCDc_L,
tCCD_S,
tCCDc_S;
int tRRD_L,
tRRDc_L,
tRRD_S,
tRRDc_S,
tRRDc_dlr,
tFAW,
tFAWc_dlr,
tIS,
tIH,
tDIPW;
int tZQinitc,
tZQoperc,
tZQCSc,
tZQRTT,
tZQRTTc;
int tRFC,
tRFCc,
tRFC1,
tRFC1c,
tRFC2,
tRFC2c,
tRFC4,
tRFC4c,
tRFCc_dlr;
int tXPR;
int tXS,
tXSc,
tXS_Fast,
tXS_Fastc,
tXSDLLc,
tCKESRc,
tCKSRE,
tCKSREc,
tCKSRX,
tCKSRXc,
tXSR;
int tXP,
tXPc,
tXPDLL,
tXPDLLc,
tCKE,
tCKEc,
tCPDEDc,
tPD,
tPDc;
int tACTPDENc,
tPREPDENc,
tREFPDENc,
tMRSPDENc,
tMRSPDEN,
tRDPDENc,
tWRPDENc,
tWRAPDENc;
int tODTHc,
tAON,
tAON_min,
tAON_max,
tAOFp,
tAOFp_min,
tAOFp_max,
tADCp,
tADCp_min,
tADCp_max;
int tAONPD,
tAONPDc,
tAONPD_min,
tAONPD_max,
tAOF,
tAOFPD,
tAOFPDc,
tAOFPD_min,
tAOFPD_max,
tAOFASp,
tAONASp_min,
tAONASp_max,
tAOFASp_min,
tAOFASp_max;
int tWLMRDc,
tWLDQSENc,
tWLS,
tWLS_nominal,
tWLSc,
tWLH,
tWLHc;
int tWLO_nominal,
tWLO_min,
tWLO_max,
tWLOE_min,
tWLOE_nominal,
tWLOE_max,
tWLOc_min,
tWLOc_max,
tWLOEc_min,
tWLOEc_max;
int tPAR_ALERT_ON_CYCLES,
tPAR_ALERT_ON,
tPAR_ALERT_ON_max,
tPAR_ALERT_OFF,
tPAR_CLOSE_BANKS,
tPAR_tRP_tRAS_adjustment,
tPAR_tRP_holdoff_adjustment;
int tPAR_ALERT_PW,
tPAR_ALERT_PW_min,
tPAR_ALERT_PW_max,
tPAR_ALERT_PWc,
tPAR_ALERT_PWc_min,
tPAR_ALERT_PWc_max;
int tCRC_ALERT,
tCRC_ALERT_min,
tCRC_ALERT_max,
tCRC_ALERT_PWc_min,
tCRC_ALERT_PWc_max,
tCRC_ALERT_PWc;
int tSDO,
tSDOc,
tSDO_max,
tSDOc_max;
int tSYNC_GEARc,
tCMD_GEARc,
tGD_TRANSITIONc;
int tMPED,
tMPEDc,
tCKMPE,
tCKMPEc,
tCKMPX,
tCKMPXc,
tMPX_H,
tXMPDLLc,
tXMPc;
int tPWRUP,
tRESET,
tRESETCKE;
int tBSCAN_Enable,
tBSCAN_Valid;
int tWLO_project,
tRP_ref_internal,
tRPc_ref_internal;
}
UTYPE_cmdtype enum{
cmdACT,
cmdPRE,
cmdWR,
cmdRD,
cmdPREA,
cmdNOP,
cmdDES,
cmdRDA,
cmdWRA,
cmdBST,
cmdREF,
cmdREFA,
cmdSREFE,
cmdSREFX,
cmdNOCLK,
cmdLMR,
cmdPDX,
cmdAPDE,
cmdPPDE,
cmdZQ }
UTYPE_alreg enum {
rAL0=0,
rALN1=1,
rALN2=2,
rALN3=3}
UTYPE_bt enum {
SEQ=0,
INT=1}
UTYPE_odi enum {
ODI_34=34,
ODI_48=48,
ODI_40=40,
ODI_RES3=3}
UTYPE_rttn enum {
RTTN_DIS=0,
RTTN_60=60,
RTTN_120=120,
RTTN_40=40,
RTTN_240=240,
RTTN_48=48,
RTTN_80=80,
RTTN_34=34}
UTYPE_rttw enum {
RTTW_DIS=0,
RTTW_120=120,
RTTW_240=240,
RTTW_Z=3,
RTTW_80=80,
RTTW_RES5=5,
RTTW_RES6=6,
RTTW_RES7=7}
UTYPE_mpr enum {
SERIAL=0,
PARALLEL=1,
STAGGERED=2,
MPR_RES3=3}
UTYPE_mprpage enum {
MPR_PATTERN=0,
MPR_PARITY=1,
MPR_MODEREG=2,
MPR_PAGE3=3}
UTYPE_delay_write_crc_dm enum {
DELAY_WRITE_4=4,
DELAY_WRITE_5=5,
DELAY_WRITE_6=6,
DELAY_WRITE_RES3=3}
UTYPE_lpasr enum {
LPASR_NORM=0,
LPASR_REDUCED=1,
LPASR_EXTENDED=2,
LPASR_AUTO=3}
UTYPE_refmode enum {
REF_1X=0,
REF_2X=1,
REF_4X=2,
REF_RES3=3,
REF_RES4=4,
REF_FLY2X=5,
REF_FLY4X=6,
REF_RES7=7}
UTYPE_caparity_latency enum {
CAPARITY_L0=0,
CAPARITY_L4=4,
CAPARITY_L5=5,
CAPARITY_L6=6,
CAPARITY_L8=8,
CAPARITY_RES5,
CAPARITY_RES6,
CAPARITY_RES7}
UTYPE_rttp enum {
RTTP_DIS=0,
RTTP_60=60,
RTTP_120=120,
RTTP_40=40,
RTTP_34=34,
RTTP_48=48,
RTTP_80=80,
RTTP_240=240}
UTYPE_vrefdqrange enum {
VREF_DQ_RANGE1=0,
VREF_DQ_RANGE2=1}
UTYPE_DutModeConfig struct packed {
UTYPE_blreg BL_reg;
int BL;
UTYPE_bt BT;
int CL;
bit DLL_reset;
int write_recovery;
bit DLL_enable;
UTYPE_odi ODI;
UTYPE_alreg AL_reg;
int AL;
bit write_levelization;
UTYPE_rttn rtt_nominal;
bit tDQS;
bit qOff;
int CWL;
UTYPE_lpasr LPASR;
UTYPE_rttw rtt_write;
bit write_crc_enable;
bit trr_enable;
int trr_ba;
int trr_bg;
UTYPE_mprpage MPR_page;
bit MPR_enable;
bit gear_down;
bit perdram_addr;
bit temp_sense_enable;
UTYPE_refmode refresh_mode;
UTYPE_delay_write_crc_dm delay_write_crc_dm;
UTYPE_mpr MPR_mode;
bit DCC;
bit MPS;
bit TCR_range;
bit TCR_mode;
bit vref_monitor;
int CAL;
bit fast_self_refresh;
bit preamble_training;
int rd_preamble_clocks;
int wr_preamble_clocks;
bit ppr_enable;
UTYPE_caparity_latency CA_parity_latency;
bit crc_error;
bit CA_parity_error;
bit odt_buffer_disable;
UTYPE_rttp rtt_park;
bit sticky_parity_error;
bit dm_enable;
bit latched_dm_enable;
bit write_dbi;
bit latched_write_dbi;
bit read_dbi;
bit latched_read_dbi;
bit dll_frozen;
int vref_training_offset;
bit vref_training_range;
bit vref_training;
int tCCD_L;
int RL,
WL_calculated;
}
UTYPE_density enum {
_2G=2,
_4G=4,
_8G=8,
_16G=16}
UTYPE_archtype enum {
DDR4,
PRE_DDR5}
UTYPE_dutconfig struct packed{
UTYPE_archtype arch_type;
UTYPE_density density;
int by_mode;
int banks_per_group;
int bank_mask;
int bank_groups;
int bank_group_mask;
int ranks;
int banks_per_rank;
int rank_mask;
int row_addr_bits;
int row_cmd_bits;
int row_bits;
int row_mask;
int row_addr_mask;
int col_mask;
logic[MAX_DQ_BITS-1:0] dq_mask;
int num_dqs;
logic[MAX_DQS_BITS-1:0] dqs_mask;
int num_dqss;
logic[MAX_DM_BITS-1:0] dm_mask;
int num_dms;
int min_CL,
max_CL;
int max_CL_dbi_enabled,
max_CL_dbi_disabled,
min_CL_dbi_enabled,
min_CL_dbi_disabled;
int min_CWL,
max_CWL;
int min_CL_dll_off,
max_CL_dll_off;
int min_CAL,
max_CAL;
bit CAL_feature;
bit tDQS_feature;
bit LPASR_feature;
bit gear_down_feature;
bit trr_feature;
bit ppr_feature;
bit write_crc_feature;
bit write_dbi_feature;
bit read_dbi_feature;
bit dm_enable_feature;
bit rd_preamble_clocks_feature;
bit wr_preamble_clocks_feature;
bit preamble_training_feature;
bit TCR_feature;
bit MPS_feature;
bit perdram_addr_feature;
bit refresh_mode_feature;
bit parity_error_feature;
bit CA_parity_latency_feature;
int max_CA_parity_latency;
bit crc_error_feature;
bit parity_alert_feature;
bit sticky_parity_error_feature;
bit temp_sense_feature;
bit rtt_park_feature;
bit dll_frozen_feature;
bit cl_17_19_21_feature;
bit cl_a12_feature;
bit extended_wr;
bit ignore_dbi_with_mpr;
}

Functions