Entity: i2cRegTb
- File: i2cRegTb.vhd
Diagram
Description
Company : SLAC National Accelerator Laboratory
Description: Simulation testbed for i2cReg
This file is part of 'SLAC Firmware Standard Library'. It is subject to the license terms in the LICENSE.txt file found in the top-level directory of this distribution and at: https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. No part of 'SLAC Firmware Standard Library', including this file, may be copied, modified, propagated, or distributed except according to
the terms contained in the LICENSE.txt file.
Signals
| Name | Type | Description |
|---|---|---|
| masterClk | sl | |
| masterRst | sl | |
| slaveClk | slv(15 downto 0) | |
| slaveRst | slv(15 downto 0) | |
| regIn | i2cRegMasterInType | |
| regOut | i2cRegMasterOutType | |
| i2ci | i2c_in_type | |
| i2co | i2c_out_type | |
| i2cSda | sl | |
| i2cScl | sl |
Constants
| Name | Type | Value | Description |
|---|---|---|---|
| TPD_C | time | 1 ns |
Processes
- sim: ( )
Instantiations
- ClkRst_Master: surf.ClkRst
- i2cRegMaster_1: surf.i2cRegMaster
Description
Instantiate Master
- ClkRst_Slave: surf.ClkRst
Description
Slaves
Instantiate 16 Ram slaves on the bus with varying address and data sizes, and varying i2c
addresses and clock speeds.
gen_i : for i in 0 to 3 generate
gen_j : for j in 0 to 3 generate
ClkRst_Slave : entity surf.ClkRst
generic map (
CLK_PERIOD_G => (8+i)* 1 ns,
CLK_DELAY_G => j * 1 ns,
RST_START_DELAY_G => 0 ns,
RST_HOLD_TIME_G => 5 us,
SYNC_RESET_G => true)
port map (
clkP => slaveClk(i4+j),
clkN => open,
rst => slaveRst(i4+j),
rstL => open);
i2cRamSlave_1 : entity surf.i2cRamSlave
generic map (
TPD_G => TPD_C,
I2C_ADDR_G => (i4+j)4+9,
TENBIT_G => 0, --(j = 3),
FILTER_G => 10, --integer((50.0 / (8.0+i)) + 2.0),
ADDR_SIZE_G => i+1,
DATA_SIZE_G => j+1,
ENDIANNESS_G => 0) --i = 2 or i = 3)
port map (
clk => slaveClk(i4+j),
rst => slaveRst(i4+j),
i2cSda => i2cSda,
i2cScl => i2cScl);
end generate gen_j;
end generate gen_i;
- i2cRamSlave_1: surf.i2cRamSlave