Package: std_logic_misc

File: std_logic_misc.vhdl

Description

library SYNOPSYS;
use SYNOPSYS.attributes.all;

Types

Name	Type	Description
STRENGTH	(strn_X01, strn_X0H, strn_XL1, strn_X0Z, strn_XZ1, strn_WLH, strn_WLZ, strn_WZH, strn_W0H, strn_WL1)
MINOMAX		synopsys synthesis_off

Functions

strength_map (input: STD_ULOGIC;
strn: STRENGTH) return STD_LOGIC

Description

functions for mapping the STD_(U)LOGIC according to STRENGTH

strength_map_z (input:STD_ULOGIC;
strn:STRENGTH) return STD_LOGIC

Drive (V: STD_ULOGIC_VECTOR) return STD_LOGIC_VECTOR

Description

conversion functions for STD_ULOGIC_VECTOR and STD_LOGIC_VECTOR

synopsys synthesis_on

Drive (V: STD_LOGIC_VECTOR) return STD_ULOGIC_VECTOR

Sense (V: STD_ULOGIC;
vZ,
vU,
vDC: STD_ULOGIC) return STD_LOGIC

Description
synopsys synthesis_off

attribute CLOSELY_RELATED_TCF of Drive: function is TRUE;

conversion functions for sensing various types
(the second argument allows the user to specify the value to
be returned when the network is undriven)

Sense (V: STD_ULOGIC_VECTOR;
vZ,
vU,
vDC: STD_ULOGIC) return STD_LOGIC_VECTOR

Sense (V: STD_ULOGIC_VECTOR;
vZ,
vU,
vDC: STD_ULOGIC) return STD_ULOGIC_VECTOR

Sense (V: STD_LOGIC_VECTOR;
vZ,
vU,
vDC: STD_ULOGIC) return STD_LOGIC_VECTOR

Sense (V: STD_LOGIC_VECTOR;
vZ,
vU,
vDC: STD_ULOGIC) return STD_ULOGIC_VECTOR

STD_LOGIC_VECTORtoBIT_VECTOR (V: STD_LOGIC_VECTOR ;
vX,
vZ,
vU,
vDC: BIT := '0';
Xflag,
Zflag,
Uflag,
DCflag: BOOLEAN := FALSE ) return BIT_VECTOR

Description

synopsys synthesis_on

Function: STD_LOGIC_VECTORtoBIT_VECTOR STD_ULOGIC_VECTORtoBIT_VECTOR

Purpose: Conversion fun. from STD_(U)LOGIC_VECTOR to BIT_VECTOR

Mapping:    0, L --> 0
        1, H --> 1
        X, W --> vX if Xflag is TRUE
        X, W --> 0  if Xflag is FALSE
        Z --> vZ if Zflag is TRUE
        Z --> 0  if Zflag is FALSE
        U --> vU if Uflag is TRUE
        U --> 0  if Uflag is FALSE
        - --> vDC if DCflag is TRUE
        - --> 0  if DCflag is FALSE

STD_ULOGIC_VECTORtoBIT_VECTOR (V: STD_ULOGIC_VECTOR ;
vX,
vZ,
vU,
vDC: BIT := '0';
Xflag,
Zflag,
Uflag,
DCflag: BOOLEAN := FALSE ) return BIT_VECTOR

STD_ULOGICtoBIT (V: STD_ULOGIC ;
vX,
vZ,
vU,
vDC: BIT := '0';
Xflag,
Zflag,
Uflag,
DCflag: BOOLEAN := FALSE ) return BIT

Description

Function: STD_ULOGICtoBIT

Purpose: Conversion function from STD_(U)LOGIC to BIT

Mapping:    0, L --> 0
        1, H --> 1
        X, W --> vX if Xflag is TRUE
        X, W --> 0  if Xflag is FALSE
        Z --> vZ if Zflag is TRUE
        Z --> 0  if Zflag is FALSE
        U --> vU if Uflag is TRUE
        U --> 0  if Uflag is FALSE
        - --> vDC if DCflag is TRUE
        - --> 0  if DCflag is FALSE

AND_REDUCE (ARG: STD_LOGIC_VECTOR) return UX01

Description

NAND_REDUCE (ARG: STD_LOGIC_VECTOR) return UX01

OR_REDUCE (ARG: STD_LOGIC_VECTOR) return UX01

NOR_REDUCE (ARG: STD_LOGIC_VECTOR) return UX01

XOR_REDUCE (ARG: STD_LOGIC_VECTOR) return UX01

XNOR_REDUCE (ARG: STD_LOGIC_VECTOR) return UX01

AND_REDUCE (ARG: STD_ULOGIC_VECTOR) return UX01

NAND_REDUCE (ARG: STD_ULOGIC_VECTOR) return UX01

OR_REDUCE (ARG: STD_ULOGIC_VECTOR) return UX01

NOR_REDUCE (ARG: STD_ULOGIC_VECTOR) return UX01

XOR_REDUCE (ARG: STD_ULOGIC_VECTOR) return UX01

XNOR_REDUCE (ARG: STD_ULOGIC_VECTOR) return UX01

fun_BUF3S (Input,
Enable: UX01;
Strn: STRENGTH) return STD_LOGIC

Description
synopsys synthesis_off

fun_BUF3SL (Input,
Enable: UX01;
Strn: STRENGTH) return STD_LOGIC

fun_MUX2x1 (Input0,
Input1,
Sel: UX01) return UX01

fun_MAJ23 (Input0,
Input1,
Input2: UX01) return UX01

fun_WiredX (Input0,
Input1: std_ulogic) return STD_LOGIC