Entity: eth_mac_phy_10g_fifo

Diagram

DATA_WIDTH HDR_WIDTH AXIS_DATA_WIDTH AXIS_KEEP_ENABLE AXIS_KEEP_WIDTH ENABLE_PADDING ENABLE_DIC MIN_FRAME_LENGTH BIT_REVERSE SCRAMBLER_DISABLE PRBS31_ENABLE TX_SERDES_PIPELINE RX_SERDES_PIPELINE BITSLIP_HIGH_CYCLES BITSLIP_LOW_CYCLES COUNT_125US TX_FIFO_DEPTH TX_FIFO_PIPELINE_OUTPUT TX_FRAME_FIFO TX_DROP_OVERSIZE_FRAME TX_DROP_BAD_FRAME TX_DROP_WHEN_FULL RX_FIFO_DEPTH RX_FIFO_PIPELINE_OUTPUT RX_FRAME_FIFO RX_DROP_OVERSIZE_FRAME RX_DROP_BAD_FRAME RX_DROP_WHEN_FULL PTP_PERIOD_NS PTP_PERIOD_FNS PTP_USE_SAMPLE_CLOCK TX_PTP_TS_ENABLE RX_PTP_TS_ENABLE TX_PTP_TS_FIFO_DEPTH RX_PTP_TS_FIFO_DEPTH PTP_TS_WIDTH TX_PTP_TAG_ENABLE PTP_TAG_WIDTH KEEP_WIDTH wire rx_clk wire rx_rst wire tx_clk wire tx_rst wire logic_clk wire logic_rst wire ptp_sample_clk wire [AXIS_DATA_WIDTH-1:0] tx_axis_tdata wire [AXIS_KEEP_WIDTH-1:0] tx_axis_tkeep wire tx_axis_tvalid wire tx_axis_tlast wire tx_axis_tuser wire [PTP_TAG_WIDTH-1:0] s_axis_tx_ptp_ts_tag wire s_axis_tx_ptp_ts_valid wire m_axis_tx_ptp_ts_ready wire rx_axis_tready wire m_axis_rx_ptp_ts_ready wire [DATA_WIDTH-1:0] serdes_rx_data wire [HDR_WIDTH-1:0] serdes_rx_hdr wire [PTP_TS_WIDTH-1:0] ptp_ts_96 wire ptp_ts_step wire [7:0] ifg_delay wire tx_prbs31_enable wire rx_prbs31_enable wire tx_axis_tready wire s_axis_tx_ptp_ts_ready wire [PTP_TS_WIDTH-1:0] m_axis_tx_ptp_ts_96 wire [PTP_TAG_WIDTH-1:0] m_axis_tx_ptp_ts_tag wire m_axis_tx_ptp_ts_valid wire [AXIS_DATA_WIDTH-1:0] rx_axis_tdata wire [AXIS_KEEP_WIDTH-1:0] rx_axis_tkeep wire rx_axis_tvalid wire rx_axis_tlast wire rx_axis_tuser wire [PTP_TS_WIDTH-1:0] m_axis_rx_ptp_ts_96 wire m_axis_rx_ptp_ts_valid wire [DATA_WIDTH-1:0] serdes_tx_data wire [HDR_WIDTH-1:0] serdes_tx_hdr wire serdes_rx_bitslip wire tx_error_underflow wire tx_fifo_overflow wire tx_fifo_bad_frame wire tx_fifo_good_frame wire rx_error_bad_frame wire rx_error_bad_fcs wire rx_bad_block wire rx_block_lock wire rx_high_ber wire rx_fifo_overflow wire rx_fifo_bad_frame wire rx_fifo_good_frame

Description

Language: Verilog 2001

Generics

Generic name Type Value Description
DATA_WIDTH 64
HDR_WIDTH undefined
AXIS_DATA_WIDTH DATA_WIDTH
AXIS_KEEP_ENABLE undefined
AXIS_KEEP_WIDTH undefined
ENABLE_PADDING 1
ENABLE_DIC 1
MIN_FRAME_LENGTH 64
BIT_REVERSE 0
SCRAMBLER_DISABLE 0
PRBS31_ENABLE 0
TX_SERDES_PIPELINE 0
RX_SERDES_PIPELINE 0
BITSLIP_HIGH_CYCLES 1
BITSLIP_LOW_CYCLES 8
COUNT_125US 125000/6.4
TX_FIFO_DEPTH 4096
TX_FIFO_PIPELINE_OUTPUT 2
TX_FRAME_FIFO 1
TX_DROP_OVERSIZE_FRAME TX_FRAME_FIFO
TX_DROP_BAD_FRAME TX_DROP_OVERSIZE_FRAME
TX_DROP_WHEN_FULL 0
RX_FIFO_DEPTH 4096
RX_FIFO_PIPELINE_OUTPUT 2
RX_FRAME_FIFO 1
RX_DROP_OVERSIZE_FRAME RX_FRAME_FIFO
RX_DROP_BAD_FRAME RX_DROP_OVERSIZE_FRAME
RX_DROP_WHEN_FULL RX_DROP_OVERSIZE_FRAME
PTP_PERIOD_NS 4'h6
PTP_PERIOD_FNS 16'h6666
PTP_USE_SAMPLE_CLOCK 0
TX_PTP_TS_ENABLE 0
RX_PTP_TS_ENABLE 0
TX_PTP_TS_FIFO_DEPTH 64
RX_PTP_TS_FIFO_DEPTH 64
PTP_TS_WIDTH 96
TX_PTP_TAG_ENABLE 0
PTP_TAG_WIDTH 16
KEEP_WIDTH DATA_WIDTH/8

Ports

Port name Direction Type Description
rx_clk input wire
rx_rst input wire
tx_clk input wire
tx_rst input wire
logic_clk input wire
logic_rst input wire
ptp_sample_clk input wire
tx_axis_tdata input wire [AXIS_DATA_WIDTH-1:0] * AXI input */
tx_axis_tkeep input wire [AXIS_KEEP_WIDTH-1:0]
tx_axis_tvalid input wire
tx_axis_tready output wire
tx_axis_tlast input wire
tx_axis_tuser input wire
s_axis_tx_ptp_ts_tag input wire [PTP_TAG_WIDTH-1:0] * Transmit timestamp tag input */
s_axis_tx_ptp_ts_valid input wire
s_axis_tx_ptp_ts_ready output wire
m_axis_tx_ptp_ts_96 output wire [PTP_TS_WIDTH-1:0] * Transmit timestamp output */
m_axis_tx_ptp_ts_tag output wire [PTP_TAG_WIDTH-1:0]
m_axis_tx_ptp_ts_valid output wire
m_axis_tx_ptp_ts_ready input wire
rx_axis_tdata output wire [AXIS_DATA_WIDTH-1:0] * AXI output */
rx_axis_tkeep output wire [AXIS_KEEP_WIDTH-1:0]
rx_axis_tvalid output wire
rx_axis_tready input wire
rx_axis_tlast output wire
rx_axis_tuser output wire
m_axis_rx_ptp_ts_96 output wire [PTP_TS_WIDTH-1:0] * Receive timestamp output */
m_axis_rx_ptp_ts_valid output wire
m_axis_rx_ptp_ts_ready input wire
serdes_tx_data output wire [DATA_WIDTH-1:0] * SERDES interface */
serdes_tx_hdr output wire [HDR_WIDTH-1:0]
serdes_rx_data input wire [DATA_WIDTH-1:0]
serdes_rx_hdr input wire [HDR_WIDTH-1:0]
serdes_rx_bitslip output wire
tx_error_underflow output wire * Status */
tx_fifo_overflow output wire
tx_fifo_bad_frame output wire
tx_fifo_good_frame output wire
rx_error_bad_frame output wire
rx_error_bad_fcs output wire
rx_bad_block output wire
rx_block_lock output wire
rx_high_ber output wire
rx_fifo_overflow output wire
rx_fifo_bad_frame output wire
rx_fifo_good_frame output wire
ptp_ts_96 input wire [PTP_TS_WIDTH-1:0] * PTP clock */
ptp_ts_step input wire
ifg_delay input wire [7:0] * Configuration */
tx_prbs31_enable input wire
rx_prbs31_enable input wire

Signals

Name Type Description
tx_fifo_axis_tdata wire [DATA_WIDTH-1:0]
tx_fifo_axis_tkeep wire [KEEP_WIDTH-1:0]
tx_fifo_axis_tvalid wire
tx_fifo_axis_tready wire
tx_fifo_axis_tlast wire
tx_fifo_axis_tuser wire [TX_USER_WIDTH-1:0]
tx_axis_tdata_int wire [AXIS_DATA_WIDTH-1:0]
tx_axis_tkeep_int wire [AXIS_KEEP_WIDTH-1:0]
tx_axis_tvalid_int wire
tx_axis_tready_int wire
tx_axis_tlast_int wire
tx_axis_tuser_int wire [TX_USER_WIDTH-1:0]
rx_fifo_axis_tdata wire [DATA_WIDTH-1:0]
rx_fifo_axis_tkeep wire [KEEP_WIDTH-1:0]
rx_fifo_axis_tvalid wire
rx_fifo_axis_tlast wire
rx_fifo_axis_tuser wire [RX_USER_WIDTH-1:0]
rx_axis_tuser_int wire [RX_USER_WIDTH-1:0]
tx_ptp_ts_96 wire [PTP_TS_WIDTH-1:0]
rx_ptp_ts_96 wire [PTP_TS_WIDTH-1:0]
tx_axis_ptp_ts_96 wire [PTP_TS_WIDTH-1:0]
tx_axis_ptp_ts_tag wire [PTP_TAG_WIDTH-1:0]
tx_axis_ptp_ts_valid wire
rx_axis_ptp_ts_96 wire [PTP_TS_WIDTH-1:0]
rx_axis_ptp_ts_valid wire
tx_error_underflow_int wire synchronize MAC status signals into logic clock domain
tx_sync_reg_1 reg [0:0]
tx_sync_reg_2 reg [0:0]
tx_sync_reg_3 reg [0:0]
tx_sync_reg_4 reg [0:0]
rx_error_bad_frame_int wire
rx_error_bad_fcs_int wire
rx_sync_reg_1 reg [4:0]
rx_sync_reg_2 reg [4:0]
rx_sync_reg_3 reg [4:0]
rx_sync_reg_4 reg [4:0]

Constants

Name Type Value Description
TX_USER_WIDTH + 1
RX_USER_WIDTH + 1

Processes

Type: always

Type: always

Type: always

Type: always

Instantiations