Entity: eth_mac_phy_10g_rx

Diagram

DATA_WIDTH KEEP_WIDTH HDR_WIDTH PTP_PERIOD_NS PTP_PERIOD_FNS PTP_TS_ENABLE PTP_TS_WIDTH USER_WIDTH BIT_REVERSE SCRAMBLER_DISABLE PRBS31_ENABLE SERDES_PIPELINE BITSLIP_HIGH_CYCLES BITSLIP_LOW_CYCLES COUNT_125US wire clk wire rst wire [DATA_WIDTH-1:0] serdes_rx_data wire [HDR_WIDTH-1:0] serdes_rx_hdr wire [PTP_TS_WIDTH-1:0] ptp_ts wire rx_prbs31_enable wire [DATA_WIDTH-1:0] m_axis_tdata wire [KEEP_WIDTH-1:0] m_axis_tkeep wire m_axis_tvalid wire m_axis_tlast wire [USER_WIDTH-1:0] m_axis_tuser wire serdes_rx_bitslip wire [1:0] rx_start_packet wire [6:0] rx_error_count wire rx_error_bad_frame wire rx_error_bad_fcs wire rx_bad_block wire rx_block_lock wire rx_high_ber

Description

Language: Verilog 2001

Generics

Generic name Type Value Description
DATA_WIDTH 64
KEEP_WIDTH undefined
HDR_WIDTH undefined
PTP_PERIOD_NS 4'h6
PTP_PERIOD_FNS 16'h6666
PTP_TS_ENABLE 0
PTP_TS_WIDTH 96
USER_WIDTH + 1
BIT_REVERSE 0
SCRAMBLER_DISABLE 0
PRBS31_ENABLE 0
SERDES_PIPELINE 0
BITSLIP_HIGH_CYCLES 1
BITSLIP_LOW_CYCLES 8
COUNT_125US 125000/6.4

Ports

Port name Direction Type Description
clk input wire
rst input wire
m_axis_tdata output wire [DATA_WIDTH-1:0] * AXI output */
m_axis_tkeep output wire [KEEP_WIDTH-1:0]
m_axis_tvalid output wire
m_axis_tlast output wire
m_axis_tuser output wire [USER_WIDTH-1:0]
serdes_rx_data input wire [DATA_WIDTH-1:0] * SERDES interface */
serdes_rx_hdr input wire [HDR_WIDTH-1:0]
serdes_rx_bitslip output wire
ptp_ts input wire [PTP_TS_WIDTH-1:0] * PTP */
rx_start_packet output wire [1:0] * Status */
rx_error_count output wire [6:0]
rx_error_bad_frame output wire
rx_error_bad_fcs output wire
rx_bad_block output wire
rx_block_lock output wire
rx_high_ber output wire
rx_prbs31_enable input wire * Configuration */

Signals

Name Type Description
encoded_rx_data wire [DATA_WIDTH-1:0]
encoded_rx_hdr wire [HDR_WIDTH-1:0]

Instantiations