Entity: eth_phy_10g_rx

Diagram

DATA_WIDTH CTRL_WIDTH HDR_WIDTH BIT_REVERSE SCRAMBLER_DISABLE PRBS31_ENABLE SERDES_PIPELINE BITSLIP_HIGH_CYCLES BITSLIP_LOW_CYCLES COUNT_125US wire clk wire rst wire [DATA_WIDTH-1:0] serdes_rx_data wire [HDR_WIDTH-1:0] serdes_rx_hdr wire rx_prbs31_enable wire [DATA_WIDTH-1:0] xgmii_rxd wire [CTRL_WIDTH-1:0] xgmii_rxc wire serdes_rx_bitslip wire [6:0] rx_error_count wire rx_bad_block wire rx_block_lock wire rx_high_ber

Description

Language: Verilog 2001

Generics

Generic name Type Value Description
DATA_WIDTH 64
CTRL_WIDTH undefined
HDR_WIDTH 2
BIT_REVERSE 0
SCRAMBLER_DISABLE 0
PRBS31_ENABLE 0
SERDES_PIPELINE 0
BITSLIP_HIGH_CYCLES 1
BITSLIP_LOW_CYCLES 8
COUNT_125US 125000/6.4

Ports

Port name Direction Type Description
clk input wire
rst input wire
xgmii_rxd output wire [DATA_WIDTH-1:0] * XGMII interface */
xgmii_rxc output wire [CTRL_WIDTH-1:0]
serdes_rx_data input wire [DATA_WIDTH-1:0] * SERDES interface */
serdes_rx_hdr input wire [HDR_WIDTH-1:0]
serdes_rx_bitslip output wire
rx_error_count output wire [6:0] * Status */
rx_bad_block output wire
rx_block_lock output wire
rx_high_ber output wire
rx_prbs31_enable input wire * Configuration */

Signals

Name Type Description
encoded_rx_data wire [DATA_WIDTH-1:0]
encoded_rx_hdr wire [HDR_WIDTH-1:0]

Instantiations