Entity: eth_phy_10g_tx

Diagram

DATA_WIDTH CTRL_WIDTH HDR_WIDTH BIT_REVERSE SCRAMBLER_DISABLE PRBS31_ENABLE SERDES_PIPELINE wire clk wire rst wire [DATA_WIDTH-1:0] xgmii_txd wire [CTRL_WIDTH-1:0] xgmii_txc wire tx_prbs31_enable wire [DATA_WIDTH-1:0] serdes_tx_data wire [HDR_WIDTH-1:0] serdes_tx_hdr

Description

Language: Verilog 2001

Generics

Generic name Type Value Description
DATA_WIDTH 64
CTRL_WIDTH undefined
HDR_WIDTH 2
BIT_REVERSE 0
SCRAMBLER_DISABLE 0
PRBS31_ENABLE 0
SERDES_PIPELINE 0

Ports

Port name Direction Type Description
clk input wire
rst input wire
xgmii_txd input wire [DATA_WIDTH-1:0] * XGMII interface */
xgmii_txc input wire [CTRL_WIDTH-1:0]
serdes_tx_data output wire [DATA_WIDTH-1:0] * SERDES interface */
serdes_tx_hdr output wire [HDR_WIDTH-1:0]
tx_prbs31_enable input wire * Configuration */

Signals

Name Type Description
encoded_tx_data wire [DATA_WIDTH-1:0]
encoded_tx_hdr wire [HDR_WIDTH-1:0]

Instantiations