Entity: lfsr

Diagram

LFSR_WIDTH LFSR_POLY LFSR_CONFIG LFSR_FEED_FORWARD REVERSE DATA_WIDTH STYLE STYLE_INT STYLE_INT wire [DATA_WIDTH-1:0] data_in wire [LFSR_WIDTH-1:0] state_in wire [DATA_WIDTH-1:0] data_out wire [LFSR_WIDTH-1:0] state_out

Description

Language: Verilog 2001

Generics

Generic name Type Value Description
LFSR_WIDTH 31 width of LFSR
LFSR_POLY 31'h10000001 LFSR polynomial
LFSR_CONFIG "FIBONACCI" LFSR configuration: "GALOIS", "FIBONACCI"
LFSR_FEED_FORWARD 0 LFSR feed forward enable
REVERSE 0 bit-reverse input and output
DATA_WIDTH 8 width of data input
STYLE "AUTO" implementation style: "AUTO", "LOOP", "REDUCTION"
STYLE_INT "REDUCTION" "AUTO" style is "REDUCTION" for faster simulation
STYLE_INT "LOOP" "AUTO" style is "LOOP" for better synthesis result

Ports

Port name Direction Type Description
data_in input wire [DATA_WIDTH-1:0]
state_in input wire [LFSR_WIDTH-1:0]
data_out output wire [DATA_WIDTH-1:0]
state_out output wire [LFSR_WIDTH-1:0]

Signals

Name Type Description
lfsr_mask_state reg [LFSR_WIDTH-1:0]
Fully parametrizable combinatorial parallel LFSR/CRC module. Implements an unrolled LFSR next state computation, shifting DATA_WIDTH bits per pass through the module. Input data is XORed with LFSR feedback path, tie data_in to zero if this is not required.
Works in two parts: statically computes a set of bit masks, then uses these bit masks to select bits for XORing to compute the next state.
Ports:
data_in
Data bits to be shifted through the LFSR (DATA_WIDTH bits)
state_in
LFSR/CRC current state input (LFSR_WIDTH bits)
data_out
Data bits shifted out of LFSR (DATA_WIDTH bits)
state_out
LFSR/CRC next state output (LFSR_WIDTH bits)
Parameters:
LFSR_WIDTH
Specify width of LFSR/CRC register
LFSR_POLY
Specify the LFSR/CRC polynomial in hex format. For example, the polynomial
x^32 + x^26 + x^23 + x^22 + x^16 + x^12 + x^11 + x^10 + x^8 + x^7 + x^5 + x^4 + x^2 + x + 1
would be represented as
32'h04c11db7
Note that the largest term (x^32) is suppressed. This term is generated automatically based on LFSR_WIDTH.
LFSR_CONFIG
Specify the LFSR configuration, either Fibonacci or Galois. Fibonacci is generally used for linear-feedback shift registers (LFSR) for pseudorandom binary sequence (PRBS) generators, scramblers, and descrambers, while Galois is generally used for cyclic redundancy check generators and checkers.
Fibonacci style (example for 64b66b scrambler, 0x8000000001)
DIN (LSB first)
lfsr_mask_data reg [DATA_WIDTH-1:0]
output_mask_state reg [LFSR_WIDTH-1:0]
output_mask_data reg [DATA_WIDTH-1:0]
state_val reg [LFSR_WIDTH-1:0]
data_val reg [DATA_WIDTH-1:0]
i integer
j integer
k integer