Entity: ssio_ddr_in
Diagram
Description
Generics
| Generic name |
Type |
Value |
Description |
| TARGET |
|
"GENERIC" |
target ("SIM", "GENERIC", "XILINX", "ALTERA") |
| IODDR_STYLE |
|
"IODDR2" |
IODDR style ("IODDR", "IODDR2") Use IODDR for Virtex-4, Virtex-5, Virtex-6, 7 Series, Ultrascale Use IODDR2 for Spartan-6 |
| CLOCK_INPUT_STYLE |
|
"BUFG" |
Clock input style ("BUFG", "BUFR", "BUFIO", "BUFIO2") Use BUFR for Virtex-6, 7-series Use BUFG for Virtex-5, Spartan-6, Ultrascale |
| WIDTH |
|
1 |
Width of register in bits |
Ports
| Port name |
Direction |
Type |
Description |
| input_clk |
input |
wire |
|
| input_d |
input |
wire [WIDTH-1:0] |
|
| output_clk |
output |
wire |
|
| output_q1 |
output |
wire [WIDTH-1:0] |
|
| output_q2 |
output |
wire [WIDTH-1:0] |
|
Signals
| Name |
Type |
Description |
| clk_int |
wire |
|
| clk_io |
wire |
|
Instantiations