Entity: xgmii_interleave
- File: xgmii_interleave.v
Diagram
Description
Language: Verilog 2001
Ports
| Port name | Direction | Type | Description |
|---|---|---|---|
| input_xgmii_d | input | wire [63:0] | |
| input_xgmii_c | input | wire [7:0] | |
| output_xgmii_dc | output | wire [72:0] |
Language: Verilog 2001
| Port name | Direction | Type | Description |
|---|---|---|---|
| input_xgmii_d | input | wire [63:0] | |
| input_xgmii_c | input | wire [7:0] | |
| output_xgmii_dc | output | wire [72:0] |