Entity: ad7401
- File: ad7401.v
Diagram
Description
Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
In this HDL repository, there are many different and unique modules, consisting of various HDL (Verilog or VHDL) components. The individual modules are developed independently, and may be accompanied by separate and unique license terms.
The user should read each of these license terms, and understand the freedoms and responsibilities that he or she has by using this source/core.
This core is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
Redistribution and use of source or resulting binaries, with or without modification of this file, are permitted under one of the following two license terms:
- The GNU General Public License version 2 as published by the Free Software Foundation, which can be found in the top level directory of this repository (LICENSE_GPL2), and also online at: https://www.gnu.org/licenses/old-licenses/gpl-2.0.html
OR
- An ADI specific BSD license, which can be found in the top level directory of this repository (LICENSE_ADIBSD), and also on-line at: https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD This will allow to generate bit files and not release the source code, as long as it attaches to an ADI device.
Use a timescale that is best for simulation.
----------- Module Declaration -----------------------------------------------
Ports
| Port name | Direction | Type | Description |
|---|---|---|---|
| fpga_clk_i | input | system clock | |
| adc_clk_i | input | up to 20 MHZ clock | |
| reset_i | input | active high reset signal | |
| data_o | output | [15:0] | data read from the ADC |
| data_rd_ready_o | output | when set to high the data read from the ADC is available on the data_o bus | |
| adc_status_o | output | ||
| adc_mdata_i | input | AD7401 MDAT pin |
Signals
| Name | Type | Description |
|---|---|---|
| data_rdy_s | wire | ------------------------------------------------------------------------------ ----------- Wire Declarations ------------------------------------------------ ------------------------------------------------------------------------------ |
| data_s | wire [15:0] | |
| present_state | reg [3:0] | ------------------------------------------------------------------------------ ----------- Registers Declarations ------------------------------------------- ------------------------------------------------------------------------------ State machine |
| next_state | reg [3:0] | |
| data_rdy_s_d1 | reg | |
| data_rdy_s_d2 | reg |
Constants
| Name | Type | Value | Description |
|---|---|---|---|
| WAIT_DATA_RDY_HIGH_STATE | 4'b0001 | ------------------------------------------------------------------------------ ----------- Local Parameters ------------------------------------------------- ------------------------------------------------------------------------------ States | |
| ACQUIRE_DATA_STATE | 4'b0010 | ||
| TRANSFER_DATA_STATE | 4'b0100 | ||
| WAIT_DATA_RDY_LOW_STATE | 4'b1000 |
Processes
- unnamed: ( @(posedge fpga_clk_i) )
Type: always
Description
------------------------------------------------------------------------------ ----------- Assign/Always Blocks --------------------------------------------- ------------------------------------------------------------------------------ synchronize data on fpga_clki
- unnamed: ( @(posedge fpga_clk_i) )
Type: always
- unnamed: ( @(present_state, data_rdy_s_d2) )
Type: always
Instantiations
- filter: dec256sinc24b