Entity: ad_ip_jesd204_tpl_dac_framer

Diagram

NUM_LANES NUM_CHANNELS BITS_PER_SAMPLE CONVERTER_RESOLUTION SAMPLES_PER_FRAME OCTETS_PER_BEAT LINK_DATA_WIDTH DAC_DATA_WIDTH [DAC_DATA_WIDTH-1:0] dac_data [LINK_DATA_WIDTH-1:0] link_data

Description

Copyright 2018 (c) Analog Devices, Inc. All rights reserved.

Each core or library found in this collection may have its own licensing terms. The user should keep this in in mind while exploring these cores.

Redistribution and use in source and binary forms, with or without modification of this file, are permitted under the terms of either (at the option of the user):

  1. The GNU General Public License version 2 as published by the Free Software Foundation, which can be found in the top level directory, or at: https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html

OR

  1. An ADI specific BSD license as noted in the top level directory, or on-line at: https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE

Generics

Generic name Type Value Description
NUM_LANES 8
NUM_CHANNELS 4
BITS_PER_SAMPLE 16
CONVERTER_RESOLUTION 16
SAMPLES_PER_FRAME 2
OCTETS_PER_BEAT 4
LINK_DATA_WIDTH OCTETS_PER_BEAT * 8 * NUM_LANES
DAC_DATA_WIDTH LINK_DATA_WIDTH * CONVERTER_RESOLUTION / BITS_PER_SAMPLE

Ports

Port name Direction Type Description
link_data output [LINK_DATA_WIDTH-1:0] jesd interface
dac_data input [DAC_DATA_WIDTH-1:0] dac interface

Signals

Name Type Description
link_data_msb_s wire [LINK_DATA_WIDTH-1:0]
frame_data_s wire [LINK_DATA_WIDTH-1:0]
dac_data_msb wire [LINK_DATA_WIDTH-1:0]

Constants

Name Type Value Description
BITS_PER_CHANNEL_PER_FRAME BITS_PER_SAMPLE * SAMPLES_PER_FRAME * The framer module takes sample data and maps it onto the format that the * JESD204 link expects for the specified framer configuration. * * The input sample data in dac_data is expected to be grouped by converter. * The first sample is in the LSBs. Each sample has CONVERTER_RESOLUTION bits. * * Or in other words the data in dac_data is expected to have the following * layout. * * MSB LSB * [ MmSn, …, MmS1, MnS0, …, M1Sn, … M1S1, M1S0, M0Sn, … M0S1, M0S0 ] * * Where MjSi refers to the i-th sample of the j-th converter. With m being * the number of converters and n the number of samples per converter per * beat. * * In the default configuration the framer module processes 4 octets per beat. * This means it can support settings with either 1, 2 or 4 octets per frame * (F). Depending on the octets per frame the frames per beat will either be * 4, 2 or 1 respectively. For other settings of OCTETS_PER_BEAT similar * reasoning applies. * * The number of samples per frame (S) and the number of frames processed per * beat gives the number of samples per converter per beat. This is either * S * 4 (for F=1), S * 2 (for F=2) or S (for F=1). * * The framer module does not have a parameter for the octets per frame (F) * since it can be derived from all other parameters given the following * relationship: F = (M * N' * S) / (L * 8) * * * Mapping in performed in two steps. First samples are grouped into frames, * as there might be more than one frame pert beat. In the second step the * frames are distributed onto the lanes. * * In the JESD204 standard samples and octets are ordered MSB first, this * means earlier data is in the MSBs. This core on the other hand expects * samples and octets to be LSB first ordered. This means earlier data is in * the LSBs. To accommodate this two additional steps are required to order * data from LSB to MSB before the framing process and back from MSB to LSB * after it. * * The data itself that is contained within the samples and octets is LSB * ordered in either case. That means lower bits are in the LSBs. */
BITS_PER_LANE_PER_FRAME BITS_PER_CHANNEL_PER_FRA
FRAMES_PER_BEAT OCTETS_PER_BEAT * 8 / BITS_PER_LANE_PER_FRAME
SAMPLES_PER_BEAT DAC_DATA_WIDTH / CONVERTER_RESOLUTION
TAIL_BITS BITS_PER_SAMPLE - CONVERTER_RESOLUTION