Entity: ad_ss_422to444
- File: ad_ss_422to444.v
Diagram
Description
Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
In this HDL repository, there are many different and unique modules, consisting of various HDL (Verilog or VHDL) components. The individual modules are developed independently, and may be accompanied by separate and unique license terms.
The user should read each of these license terms, and understand the freedoms and responsibilities that he or she has by using this source/core.
This core is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
Redistribution and use of source or resulting binaries, with or without modification of this file, are permitted under one of the following two license terms:
- The GNU General Public License version 2 as published by the Free Software Foundation, which can be found in the top level directory of this repository (LICENSE_GPL2), and also online at: https://www.gnu.org/licenses/old-licenses/gpl-2.0.html
OR
- An ADI specific BSD license, which can be found in the top level directory of this repository (LICENSE_ADIBSD), and also on-line at: https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD This will allow to generate bit files and not release the source code, as long as it attaches to an ADI device.
Input must be RGB or CrYCb in that order, output is CrY/CbY
Generics
| Generic name | Type | Value | Description |
|---|---|---|---|
| CR_CB_N | 0 | ||
| DELAY_DATA_WIDTH | 16 |
Ports
| Port name | Direction | Type | Description |
|---|---|---|---|
| clk | input | 422 inputs | |
| s422_de | input | ||
| s422_sync | input | [DELAY_DATA_WIDTH-1:0] | |
| s422_data | input | [ 15:0] | |
| s444_sync | output | [DELAY_DATA_WIDTH-1:0] | 444 outputs |
| s444_data | output | [ 23:0] |
Signals
| Name | Type | Description |
|---|---|---|
| cr_cb_sel | reg | internal registers |
| s422_de_d | reg | |
| s422_sync_d | reg [DW:0] | |
| s422_de_2d | reg | |
| s422_Y_d | reg [7:0] | |
| s422_CbCr_d | reg [7:0] | |
| s422_CbCr_2d | reg [7:0] | |
| s422_CbCr_avg | reg [ 8:0] | |
| s422_Y | wire [ 7:0] | internal wires |
| s422_CbCr | wire [ 7:0] |
Constants
| Name | Type | Value | Description |
|---|---|---|---|
| DW | DELAY_DATA_WIDTH - 1 |
Processes
- unnamed: ( @(posedge clk) )
Type: always
Description
first data on de assertion is cb (0x0), then cr (0x1). previous data is held when not current
- unnamed: ( @(posedge clk) )
Type: always
Description
pipe line stages
- unnamed: ( @(s422_de_2d, s422_de, s422_CbCr, s422_CbCr_2d) )
Type: always
Description
If both the left and the right sample are valid do the average, otherwise use the only valid.
- unnamed: ( @(posedge clk) )
Type: always
Description
444 outputs