Entity: ad_tdd_control

• File: ad_tdd_control.v

Diagram

Description

Generics

Generic name	Type	Value	Description
TX_DATA_PATH_DELAY	integer	0
CONTROL_PATH_DELAY	integer	0

Ports

Port name	Direction	Type	Description
clk	input		clock and reset
rst	input
tdd_enable	input		TDD timing signals
tdd_secondary	input
tdd_tx_only	input
tdd_rx_only	input
tdd_burst_count	input	[ 7:0]
tdd_counter_init	input	[23:0]
tdd_frame_length	input	[23:0]
tdd_vco_rx_on_1	input	[23:0]
tdd_vco_rx_off_1	input	[23:0]
tdd_vco_tx_on_1	input	[23:0]
tdd_vco_tx_off_1	input	[23:0]
tdd_rx_on_1	input	[23:0]
tdd_rx_off_1	input	[23:0]
tdd_rx_dp_on_1	input	[23:0]
tdd_rx_dp_off_1	input	[23:0]
tdd_tx_on_1	input	[23:0]
tdd_tx_off_1	input	[23:0]
tdd_tx_dp_on_1	input	[23:0]
tdd_tx_dp_off_1	input	[23:0]
tdd_vco_rx_on_2	input	[23:0]
tdd_vco_rx_off_2	input	[23:0]
tdd_vco_tx_on_2	input	[23:0]
tdd_vco_tx_off_2	input	[23:0]
tdd_rx_on_2	input	[23:0]
tdd_rx_off_2	input	[23:0]
tdd_rx_dp_on_2	input	[23:0]
tdd_rx_dp_off_2	input	[23:0]
tdd_tx_on_2	input	[23:0]
tdd_tx_off_2	input	[23:0]
tdd_tx_dp_on_2	input	[23:0]
tdd_tx_dp_off_2	input	[23:0]
tdd_sync	input
tdd_tx_dp_en	output		TDD control signals
tdd_rx_dp_en	output
tdd_rx_vco_en	output
tdd_tx_vco_en	output
tdd_rx_rf_en	output
tdd_tx_rf_en	output
tdd_counter_status	output	[23:0]

Signals

Name	Type	Description
tdd_counter	reg [23:0]	tdd control related tdd counter related
tdd_burst_counter	reg [ 5:0]
tdd_cstate	reg
tdd_cstate_next	reg
counter_at_tdd_vco_rx_on_1	reg
counter_at_tdd_vco_rx_off_1	reg
counter_at_tdd_vco_tx_on_1	reg
counter_at_tdd_vco_tx_off_1	reg
counter_at_tdd_rx_on_1	reg
counter_at_tdd_rx_off_1	reg
counter_at_tdd_rx_dp_on_1	reg
counter_at_tdd_rx_dp_off_1	reg
counter_at_tdd_tx_on_1	reg
counter_at_tdd_tx_off_1	reg
counter_at_tdd_tx_dp_on_1	reg
counter_at_tdd_tx_dp_off_1	reg
counter_at_tdd_vco_rx_on_2	reg
counter_at_tdd_vco_rx_off_2	reg
counter_at_tdd_vco_tx_on_2	reg
counter_at_tdd_vco_tx_off_2	reg
counter_at_tdd_rx_on_2	reg
counter_at_tdd_rx_off_2	reg
counter_at_tdd_rx_dp_on_2	reg
counter_at_tdd_rx_dp_off_2	reg
counter_at_tdd_tx_on_2	reg
counter_at_tdd_tx_off_2	reg
counter_at_tdd_tx_dp_on_2	reg
counter_at_tdd_tx_dp_off_2	reg
tdd_last_burst	reg
tdd_sync_d1	reg
tdd_sync_d2	reg
tdd_sync_d3	reg
tdd_endof_frame	reg
tdd_vco_rx_on_1_s	wire [23:0]	internal signals
tdd_vco_rx_off_1_s	wire [23:0]
tdd_vco_tx_on_1_s	wire [23:0]
tdd_vco_tx_off_1_s	wire [23:0]
tdd_rx_on_1_s	wire [23:0]
tdd_rx_off_1_s	wire [23:0]
tdd_tx_on_1_s	wire [23:0]
tdd_tx_off_1_s	wire [23:0]
tdd_tx_dp_on_1_s	wire [23:0]
tdd_tx_dp_off_1_s	wire [23:0]
tdd_vco_rx_on_2_s	wire [23:0]
tdd_vco_rx_off_2_s	wire [23:0]
tdd_vco_tx_on_2_s	wire [23:0]
tdd_vco_tx_off_2_s	wire [23:0]
tdd_rx_on_2_s	wire [23:0]
tdd_rx_off_2_s	wire [23:0]
tdd_tx_on_2_s	wire [23:0]
tdd_tx_off_2_s	wire [23:0]
tdd_tx_dp_on_2_s	wire [23:0]
tdd_tx_dp_off_2_s	wire [23:0]
tdd_endof_burst	wire
tdd_txrx_only_en_s	wire

Constants

Name	Type	Value	Description
ON	[ 0:0]	1
OFF	[ 0:0]	0

Processes

• unnamed: ( @(posedge clk) )

• unnamed: ( @(posedge clk) )

• unnamed: ( @* )

• unnamed: ( @(posedge clk) )

• unnamed: ( @(posedge clk) )

• unnamed: ( @(posedge clk) )

• unnamed: ( @(posedge clk) )

• unnamed: ( @(posedge clk) )

• unnamed: ( @(posedge clk) )

• unnamed: ( @(posedge clk) )

• unnamed: ( @(posedge clk) )

• unnamed: ( @(posedge clk) )

• unnamed: ( @(posedge clk) )

• unnamed: ( @(posedge clk) )

• unnamed: ( @(posedge clk) )

• unnamed: ( @(posedge clk) )

• unnamed: ( @(posedge clk) )

• unnamed: ( @(posedge clk) )

• unnamed: ( @(posedge clk) )

• unnamed: ( @(posedge clk) )

• unnamed: ( @(posedge clk) )

• unnamed: ( @(posedge clk) )

• unnamed: ( @(posedge clk) )

• unnamed: ( @(posedge clk) )

• unnamed: ( @(posedge clk) )

• unnamed: ( @(posedge clk) )

• unnamed: ( @(posedge clk) )

• unnamed: ( @(posedge clk) )

• unnamed: ( @(posedge clk) )

• unnamed: ( @(posedge clk) )

• unnamed: ( @(posedge clk) )

• unnamed: ( @(posedge clk) )

• unnamed: ( @(posedge clk) )

• unnamed: ( @(posedge clk) )

• unnamed: ( @(posedge clk) )

• unnamed: ( @(posedge clk) )

• unnamed: ( @(posedge clk) )

Instantiations

• i_vco_rx_on_1_comp: ad_addsub

• i_vco_rx_off_1_comp: ad_addsub

• i_vco_tx_on_1_comp: ad_addsub

• i_vco_tx_off_1_comp: ad_addsub

• i_rx_on_1_comp: ad_addsub

• i_rx_off_1_comp: ad_addsub

• i_tx_on_1_comp: ad_addsub

• i_tx_off_1_comp: ad_addsub

• i_vco_rx_on_2_comp: ad_addsub

• i_vco_rx_off_2_comp: ad_addsub

• i_vco_tx_on_2_comp: ad_addsub

• i_vco_tx_off_2_comp: ad_addsub

• i_rx_on_2_comp: ad_addsub

• i_rx_off_2_comp: ad_addsub

• i_tx_on_2_comp: ad_addsub

• i_tx_off_2_comp: ad_addsub

• i_tx_dp_on_1_comp: ad_addsub

• i_tx_dp_on_2_comp: ad_addsub

• i_tx_dp_off_1_comp: ad_addsub

• i_tx_dp_off_2_comp: ad_addsub