Entity: adrv9001_tx

Diagram

CMOS_LVDS_N NUM_LANES FPGA_TECHNOLOGY USE_RX_CLK_FOR_TX ref_clk up_clk mssi_sync tx_output_enable tx_dclk_in_n_NC tx_dclk_in_p_dclk_in rx_clk_div rx_clk rx_ssi_rst dac_rst [7:0] dac_data_0 [7:0] dac_data_1 [7:0] dac_data_2 [7:0] dac_data_3 [7:0] dac_data_strb [7:0] dac_data_clk dac_data_valid tx_dclk_out_n_NC tx_dclk_out_p_dclk_out tx_idata_out_n_idata0 tx_idata_out_p_idata1 tx_qdata_out_n_qdata2 tx_qdata_out_p_qdata3 tx_strobe_out_n_NC tx_strobe_out_p_strobe_out [31:0] dac_clk_ratio dac_clk_div

Description

Copyright 2014 - 2020 (c) Analog Devices, Inc. All rights reserved.

In this HDL repository, there are many different and unique modules, consisting of various HDL (Verilog or VHDL) components. The individual modules are developed independently, and may be accompanied by separate and unique license terms.

The user should read each of these license terms, and understand the freedoms and responsibilities that he or she has by using this source/core.

This core is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.

Redistribution and use of source or resulting binaries, with or without modification of this file, are permitted under one of the following two license terms:

  1. The GNU General Public License version 2 as published by the Free Software Foundation, which can be found in the top level directory of this repository (LICENSE_GPL2), and also online at: https://www.gnu.org/licenses/old-licenses/gpl-2.0.html

OR

  1. An ADI specific BSD license, which can be found in the top level directory of this repository (LICENSE_ADIBSD), and also on-line at: https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD This will allow to generate bit files and not release the source code, as long as it attaches to an ADI device.

Generics

Generic name Type Value Description
CMOS_LVDS_N 0
NUM_LANES 4
FPGA_TECHNOLOGY 0
USE_RX_CLK_FOR_TX 0

Ports

Port name Direction Type Description
ref_clk input
up_clk input
mssi_sync input
tx_output_enable input
tx_dclk_out_n_NC output physical interface (transmit)
tx_dclk_out_p_dclk_out output
tx_dclk_in_n_NC input
tx_dclk_in_p_dclk_in input
tx_idata_out_n_idata0 output
tx_idata_out_p_idata1 output
tx_qdata_out_n_qdata2 output
tx_qdata_out_p_qdata3 output
tx_strobe_out_n_NC output
tx_strobe_out_p_strobe_out output
rx_clk_div input
rx_clk input
rx_ssi_rst input
dac_clk_ratio output [31:0] internal resets and clocks
dac_rst input
dac_clk_div output
dac_data_0 input [7:0]
dac_data_1 input [7:0]
dac_data_2 input [7:0]
dac_data_3 input [7:0]
dac_data_strb input [7:0]
dac_data_clk input [7:0]
dac_data_valid input

Signals

Name Type Description
serdes_in wire [6*8-1:0]
gpio_out wire [5:0]

Instantiations