Entity: avl_dacfifo_wr
- File: avl_dacfifo_wr.v
Diagram
Description
Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
In this HDL repository, there are many different and unique modules, consisting of various HDL (Verilog or VHDL) components. The individual modules are developed independently, and may be accompanied by separate and unique license terms.
The user should read each of these license terms, and understand the freedoms and responsibilities that he or she has by using this source/core.
This core is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
Redistribution and use of source or resulting binaries, with or without modification of this file, are permitted under one of the following two license terms:
- The GNU General Public License version 2 as published by the Free Software Foundation, which can be found in the top level directory of this repository (LICENSE_GPL2), and also online at: https://www.gnu.org/licenses/old-licenses/gpl-2.0.html
OR
- An ADI specific BSD license, which can be found in the top level directory of this repository (LICENSE_ADIBSD), and also on-line at: https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD This will allow to generate bit files and not release the source code, as long as it attaches to an ADI device.
Generics
| Generic name | Type | Value | Description |
|---|---|---|---|
| AVL_DATA_WIDTH | 512 | ||
| DMA_DATA_WIDTH | 64 | ||
| AVL_BURST_LENGTH | 128 | ||
| AVL_DDR_BASE_ADDRESS | 0 | ||
| AVL_DDR_ADDRESS_LIMIT | 33554432 | ||
| DMA_MEM_ADDRESS_WIDTH | 10 |
Ports
| Port name | Direction | Type | Description |
|---|---|---|---|
| dma_clk | input | ||
| dma_data | input | [DMA_DATA_WIDTH-1:0] | |
| dma_ready | input | ||
| dma_ready_out | output | ||
| dma_valid | input | ||
| dma_xfer_req | input | ||
| dma_xfer_last | input | ||
| dma_last_beats | output | [ 7:0] | |
| avl_clk | input | ||
| avl_reset | input | ||
| avl_address | output | [24:0] | |
| avl_burstcount | output | [ 6:0] | |
| avl_byteenable | output | [63:0] | |
| avl_waitrequest | input | ||
| avl_write | output | ||
| avl_data | output | [AVL_DATA_WIDTH-1:0] | |
| avl_last_address | output | [24:0] | |
| avl_last_burstcount | output | [ 6:0] | |
| avl_xfer_req_out | output | ||
| avl_xfer_req_in | input |
Signals
| Name | Type | Description |
|---|---|---|
| dma_reset | wire | |
| dma_fifo_reset_s | wire | |
| dma_mem_wea_s | wire | |
| dma_mem_addr_diff_s | wire [DMA_MEM_ADDRESS_WIDTH :0] | |
| dma_mem_raddr_s | wire [DMA_MEM_ADDRESS_WIDTH-1:0] | |
| dma_mem_waddr_b2g_s | wire [DMA_MEM_ADDRESS_WIDTH-1:0] | |
| dma_mem_raddr_g2b_s | wire [AVL_MEM_ADDRESS_WIDTH-1:0] | |
| avl_fifo_reset_s | wire | |
| avl_write_int_s | wire | |
| avl_mem_raddr_b2g_s | wire [AVL_MEM_ADDRESS_WIDTH-1:0] | |
| avl_mem_waddr_m2_g2b_s | wire [DMA_MEM_ADDRESS_WIDTH-1:0] | |
| avl_mem_addr_diff_s | wire [AVL_MEM_ADDRESS_WIDTH-1:0] | |
| avl_mem_waddr_s | wire [AVL_MEM_ADDRESS_WIDTH:0] | |
| avl_data_s | wire [AVL_DATA_WIDTH-1:0] | |
| avl_xfer_req_lp_s | wire | |
| dma_mem_waddr | reg [DMA_MEM_ADDRESS_WIDTH-1:0] | |
| dma_mem_waddr_g | reg [DMA_MEM_ADDRESS_WIDTH-1:0] | |
| dma_mem_raddr_m1 | reg [AVL_MEM_ADDRESS_WIDTH-1:0] | |
| dma_mem_raddr_m2 | reg [AVL_MEM_ADDRESS_WIDTH-1:0] | |
| dma_mem_raddr | reg [AVL_MEM_ADDRESS_WIDTH-1:0] | |
| dma_mem_addr_diff | reg [DMA_MEM_ADDRESS_WIDTH-1:0] | |
| dma_xfer_req_d | reg | |
| dma_xfer_req_lp_m1 | reg | |
| dma_xfer_req_lp_m2 | reg | |
| dma_xfer_req_lp | reg | |
| dma_avl_xfer_req_out_m1 | reg | |
| dma_avl_xfer_req_out_m2 | reg | |
| dma_avl_xfer_req_out | reg | |
| avl_write_state | reg [ 4:0] | |
| avl_write_d | reg | |
| avl_mem_raddr | reg [AVL_MEM_ADDRESS_WIDTH-1:0] | |
| avl_mem_raddr_g | reg [AVL_MEM_ADDRESS_WIDTH-1:0] | |
| avl_mem_waddr | reg [DMA_MEM_ADDRESS_WIDTH-1:0] | |
| avl_mem_waddr_m1 | reg [DMA_MEM_ADDRESS_WIDTH-1:0] | |
| avl_mem_waddr_m2 | reg [DMA_MEM_ADDRESS_WIDTH-1:0] | |
| avl_mem_addr_diff | reg [AVL_MEM_ADDRESS_WIDTH-1:0] | |
| avl_dma_xfer_req | reg | |
| avl_dma_xfer_req_m1 | reg | |
| avl_dma_xfer_req_m2 | reg | |
| avl_dma_last_beats | reg [ 7:0] | |
| avl_dma_last_beats_m1 | reg [ 7:0] | |
| avl_dma_last_beats_m2 | reg [ 7:0] | |
| avl_xfer_pburst_offset | reg [ 3:0] | |
| avl_burst_counter | reg [ 7:0] | |
| avl_last_burst | reg | |
| avl_init_burst | reg | |
| avl_endof_burst | reg | |
| avl_mem_rvalid | reg [ 1:0] | |
| avl_xfer_req_lp | reg |
Constants
| Name | Type | Value | Description |
|---|---|---|---|
| MEM_RATIO | AVL_DATA_WIDTH/DMA_DATA_WIDTH | Max supported MEM_RATIO is 16 | |
| AVL_MEM_ADDRESS_WIDTH | |||
| DMA_BUF_THRESHOLD_HI | - AVL_BURST_LENGTH | ||
| IDLE | 5'b00001 | FSM state definition | |
| XFER_STAGING | 5'b00010 | ||
| XFER_FULL_BURST | 5'b00100 | ||
| XFER_PARTIAL_BURST | 5'b01000 | ||
| XFER_END | 5'b10000 |
Processes
- unnamed: ( @(posedge dma_clk) )
Type: always
- unnamed: ( @(posedge dma_clk) )
Type: always
- unnamed: ( @(posedge dma_clk) )
Type: always
- unnamed: ( @(posedge dma_clk) )
Type: always
- unnamed: ( @(posedge dma_clk) )
Type: always
- unnamed: ( @(posedge avl_clk) )
Type: always
- unnamed: ( @(posedge avl_clk) )
Type: always
- unnamed: ( @(posedge avl_clk) )
Type: always
Description
FSM to generate the necessary Avalon Write transactions
- unnamed: ( @(posedge avl_clk) )
Type: always
- unnamed: ( @(posedge avl_clk) )
Type: always
- unnamed: ( @(posedge avl_clk) )
Type: always
- unnamed: ( @(posedge avl_clk) )
Type: always
Description
Avalon write address
- unnamed: ( @(posedge avl_clk) )
Type: always
Description
Avalon write
- unnamed: ( @(posedge avl_clk) )
Type: always
Description
Avalon burstcount & counter
- unnamed: ( @(posedge avl_clk) )
Type: always
Description
generate avl_byteenable signal
- unnamed: ( @(posedge avl_clk) )
Type: always
Description
save the last address and byteenable
- unnamed: ( @(posedge avl_clk) )
Type: always
Description
avl_xfer_req generation for synchronize the access of the external memory
Instantiations
- i_mem_asym: ad_mem_asym_wr
Description
An asymmetric memory to transfer data from DMAC interface to Avalon Memory Map
interface
- i_dma_mem_waddr_b2g: ad_b2g
- i_dma_mem_rd_address_g2b: ad_g2b
- i_avl_mem_waddr_g2b: ad_g2b
- i_avl_mem_rd_address_b2g: ad_b2g
State machines
- FSM to generate the necessary Avalon Write transactions