Entity: axi_adrv9001_if

Diagram

CMOS_LVDS_N FPGA_TECHNOLOGY NUM_LANES DRP_WIDTH IO_DELAY_GROUP USE_RX_CLK_FOR_TX ref_clk tx_output_enable mssi_sync rx1_dclk_in_n_NC rx1_dclk_in_p_dclk_in rx1_idata_in_n_idata0 rx1_idata_in_p_idata1 rx1_qdata_in_n_qdata2 rx1_qdata_in_p_qdata3 rx1_strobe_in_n_NC rx1_strobe_in_p_strobe_in rx2_dclk_in_n_NC rx2_dclk_in_p_dclk_in rx2_idata_in_n_idata0 rx2_idata_in_p_idata1 rx2_qdata_in_n_qdata2 rx2_qdata_in_p_qdata3 rx2_strobe_in_n_NC rx2_strobe_in_p_strobe_in tx1_dclk_in_n_NC tx1_dclk_in_p_dclk_in tx2_dclk_in_n_NC tx2_dclk_in_p_dclk_in delay_clk delay_rx1_rst delay_rx2_rst up_clk [NUM_LANES-1:0] up_rx1_dld [DRP_WIDTH*NUM_LANES-1:0] up_rx1_dwdata [NUM_LANES-1:0] up_rx2_dld [DRP_WIDTH*NUM_LANES-1:0] up_rx2_dwdata rx1_rst rx1_single_lane rx1_sdr_ddr_n rx1_symb_op rx1_symb_8_16b rx2_rst rx2_single_lane rx2_sdr_ddr_n rx2_symb_op rx2_symb_8_16b tx1_rst tx1_data_valid [15:0] tx1_data_i [15:0] tx1_data_q tx1_single_lane tx1_sdr_ddr_n tx1_symb_op tx1_symb_8_16b tx2_rst tx2_data_valid [15:0] tx2_data_i [15:0] tx2_data_q tx2_single_lane tx2_sdr_ddr_n tx2_symb_op tx2_symb_8_16b tx1_dclk_out_n_NC tx1_dclk_out_p_dclk_out tx1_idata_out_n_idata0 tx1_idata_out_p_idata1 tx1_qdata_out_n_qdata2 tx1_qdata_out_p_qdata3 tx1_strobe_out_n_NC tx1_strobe_out_p_strobe_out tx2_dclk_out_n_NC tx2_dclk_out_p_dclk_out tx2_idata_out_n_idata0 tx2_idata_out_p_idata1 tx2_qdata_out_n_qdata2 tx2_qdata_out_p_qdata3 tx2_strobe_out_n_NC tx2_strobe_out_p_strobe_out delay_rx1_locked delay_rx2_locked [DRP_WIDTH*NUM_LANES-1:0] up_rx1_drdata [DRP_WIDTH*NUM_LANES-1:0] up_rx2_drdata [ 31:0] adc_clk_ratio [ 31:0] dac_clk_ratio rx1_clk rx1_data_valid [15:0] rx1_data_i [15:0] rx1_data_q rx2_clk rx2_data_valid [15:0] rx2_data_i [15:0] rx2_data_q tx1_clk tx2_clk

Description

Copyright 2014 - 2020 (c) Analog Devices, Inc. All rights reserved.

In this HDL repository, there are many different and unique modules, consisting of various HDL (Verilog or VHDL) components. The individual modules are developed independently, and may be accompanied by separate and unique license terms.

The user should read each of these license terms, and understand the freedoms and responsibilities that he or she has by using this source/core.

This core is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.

Redistribution and use of source or resulting binaries, with or without modification of this file, are permitted under one of the following two license terms:

  1. The GNU General Public License version 2 as published by the Free Software Foundation, which can be found in the top level directory of this repository (LICENSE_GPL2), and also online at: https://www.gnu.org/licenses/old-licenses/gpl-2.0.html

OR

  1. An ADI specific BSD license, which can be found in the top level directory of this repository (LICENSE_ADIBSD), and also on-line at: https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD This will allow to generate bit files and not release the source code, as long as it attaches to an ADI device.

Generics

Generic name Type Value Description
CMOS_LVDS_N 0
FPGA_TECHNOLOGY 0
NUM_LANES 3
DRP_WIDTH 5
IO_DELAY_GROUP "dev_if_delay_group"
USE_RX_CLK_FOR_TX 0

Ports

Port name Direction Type Description
ref_clk input
tx_output_enable input
mssi_sync input
rx1_dclk_in_n_NC input device interface
rx1_dclk_in_p_dclk_in input
rx1_idata_in_n_idata0 input
rx1_idata_in_p_idata1 input
rx1_qdata_in_n_qdata2 input
rx1_qdata_in_p_qdata3 input
rx1_strobe_in_n_NC input
rx1_strobe_in_p_strobe_in input
rx2_dclk_in_n_NC input
rx2_dclk_in_p_dclk_in input
rx2_idata_in_n_idata0 input
rx2_idata_in_p_idata1 input
rx2_qdata_in_n_qdata2 input
rx2_qdata_in_p_qdata3 input
rx2_strobe_in_n_NC input
rx2_strobe_in_p_strobe_in input
tx1_dclk_out_n_NC output
tx1_dclk_out_p_dclk_out output
tx1_dclk_in_n_NC input
tx1_dclk_in_p_dclk_in input
tx1_idata_out_n_idata0 output
tx1_idata_out_p_idata1 output
tx1_qdata_out_n_qdata2 output
tx1_qdata_out_p_qdata3 output
tx1_strobe_out_n_NC output
tx1_strobe_out_p_strobe_out output
tx2_dclk_out_n_NC output
tx2_dclk_out_p_dclk_out output
tx2_dclk_in_n_NC input
tx2_dclk_in_p_dclk_in input
tx2_idata_out_n_idata0 output
tx2_idata_out_p_idata1 output
tx2_qdata_out_n_qdata2 output
tx2_qdata_out_p_qdata3 output
tx2_strobe_out_n_NC output
tx2_strobe_out_p_strobe_out output
delay_clk input delay interface (for IDELAY macros)
delay_rx1_rst input
delay_rx2_rst input
delay_rx1_locked output
delay_rx2_locked output
up_clk input
up_rx1_dld input [NUM_LANES-1:0]
up_rx1_dwdata input [DRP_WIDTH*NUM_LANES-1:0]
up_rx1_drdata output [DRP_WIDTH*NUM_LANES-1:0]
up_rx2_dld input [NUM_LANES-1:0]
up_rx2_dwdata input [DRP_WIDTH*NUM_LANES-1:0]
up_rx2_drdata output [DRP_WIDTH*NUM_LANES-1:0]
adc_clk_ratio output [ 31:0] upper layer data interface
dac_clk_ratio output [ 31:0]
rx1_clk output
rx1_rst input
rx1_data_valid output
rx1_data_i output [15:0]
rx1_data_q output [15:0]
rx1_single_lane input
rx1_sdr_ddr_n input
rx1_symb_op input
rx1_symb_8_16b input
rx2_clk output
rx2_rst input
rx2_data_valid output
rx2_data_i output [15:0]
rx2_data_q output [15:0]
rx2_single_lane input
rx2_sdr_ddr_n input
rx2_symb_op input
rx2_symb_8_16b input
tx1_clk output
tx1_rst input
tx1_data_valid input
tx1_data_i input [15:0]
tx1_data_q input [15:0]
tx1_single_lane input
tx1_sdr_ddr_n input
tx1_symb_op input
tx1_symb_8_16b input
tx2_clk output
tx2_rst input
tx2_data_valid input
tx2_data_i input [15:0]
tx2_data_q input [15:0]
tx2_single_lane input
tx2_sdr_ddr_n input
tx2_symb_op input
tx2_symb_8_16b input

Signals

Name Type Description
adc_1_clk_div wire
adc_1_data_0 wire [7:0]
adc_1_data_1 wire [7:0]
adc_1_data_2 wire [7:0]
adc_1_data_3 wire [7:0]
adc_1_data_strobe wire [7:0]
adc_1_clk wire
adc_1_valid wire
adc_1_ssi_rst wire
adc_2_clk_div wire
adc_2_data_0 wire [7:0]
adc_2_data_1 wire [7:0]
adc_2_data_2 wire [7:0]
adc_2_data_3 wire [7:0]
adc_2_data_strobe wire [7:0]
adc_2_clk wire
adc_2_valid wire
adc_2_ssi_rst wire
dac_1_clk_div wire
dac_1_data_0 wire [7:0]
dac_1_data_1 wire [7:0]
dac_1_data_2 wire [7:0]
dac_1_data_3 wire [7:0]
dac_1_data_strobe wire [7:0]
dac_1_data_clk wire [7:0]
dac_1_data_valid wire
dac_2_clk_div wire
dac_2_data_0 wire [7:0]
dac_2_data_1 wire [7:0]
dac_2_data_2 wire [7:0]
dac_2_data_3 wire [7:0]
dac_2_data_strobe wire [7:0]
dac_2_data_clk wire [7:0]
dac_2_data_valid wire
rx_ssi_sync_out wire

Constants

Name Type Value Description
TX_NUM_LANES NUM_LANES + 1 Tx has an extra lane to drive the clock

Instantiations