Entity: axi_dmac_burst_memory

Diagram

DATA_WIDTH_SRC DATA_WIDTH_DEST ID_WIDTH MAX_BYTES_PER_BURST ASYNC_CLK BYTES_PER_BEAT_WIDTH_SRC BYTES_PER_BURST_WIDTH DMA_LENGTH_ALIGN ENABLE_DIAGNOSTICS_IF ALLOW_ASYM_MEM src_clk src_reset src_data_valid [DATA_WIDTH_SRC-1:0] src_data src_data_last [BYTES_PER_BEAT_WIDTH_SRC-1:0] src_data_valid_bytes src_data_partial_burst dest_clk dest_reset dest_data_ready [ID_WIDTH-1:0] dest_data_request_id [ID_WIDTH-1:0] src_data_request_id dest_data_valid [DATA_WIDTH_DEST-1:0] dest_data dest_data_last [DATA_WIDTH_DEST/8-1:0] dest_data_strb [BYTES_PER_BURST_WIDTH-1:0] dest_burst_info_length dest_burst_info_partial [ID_WIDTH-1:0] dest_burst_info_id reg dest_burst_info_write [ID_WIDTH-1:0] dest_request_id [ID_WIDTH-1:0] dest_data_response_id [7:0] dest_diag_level_bursts

Description

Copyright 2014 - 2018 (c) Analog Devices, Inc. All rights reserved.

In this HDL repository, there are many different and unique modules, consisting of various HDL (Verilog or VHDL) components. The individual modules are developed independently, and may be accompanied by separate and unique license terms.

The user should read each of these license terms, and understand the freedoms and responsibilities that he or she has by using this source/core.

This core is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.

Redistribution and use of source or resulting binaries, with or without modification of this file, are permitted under one of the following two license terms:

  1. The GNU General Public License version 2 as published by the Free Software Foundation, which can be found in the top level directory of this repository (LICENSE_GPL2), and also online at: https://www.gnu.org/licenses/old-licenses/gpl-2.0.html

OR

  1. An ADI specific BSD license, which can be found in the top level directory of this repository (LICENSE_ADIBSD), and also on-line at: https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD This will allow to generate bit files and not release the source code, as long as it attaches to an ADI device.

Generics

Generic name Type Value Description
DATA_WIDTH_SRC 64
DATA_WIDTH_DEST 64
ID_WIDTH 3
MAX_BYTES_PER_BURST 128
ASYNC_CLK 1
BYTES_PER_BEAT_WIDTH_SRC $clog2(DATA_WIDTH_SRC/8)
BYTES_PER_BURST_WIDTH $clog2(MAX_BYTES_PER_BURST)
DMA_LENGTH_ALIGN 3
ENABLE_DIAGNOSTICS_IF 0
ALLOW_ASYM_MEM 0

Ports

Port name Direction Type Description
src_clk input
src_reset input
src_data_valid input
src_data input [DATA_WIDTH_SRC-1:0]
src_data_last input
src_data_valid_bytes input [BYTES_PER_BEAT_WIDTH_SRC-1:0]
src_data_partial_burst input
src_data_request_id output [ID_WIDTH-1:0]
dest_clk input
dest_reset input
dest_data_valid output
dest_data_ready input
dest_data output [DATA_WIDTH_DEST-1:0]
dest_data_last output
dest_data_strb output [DATA_WIDTH_DEST/8-1:0]
dest_burst_info_length output [BYTES_PER_BURST_WIDTH-1:0]
dest_burst_info_partial output
dest_burst_info_id output [ID_WIDTH-1:0]
dest_burst_info_write output reg
dest_request_id output [ID_WIDTH-1:0]
dest_data_request_id input [ID_WIDTH-1:0]
dest_data_response_id output [ID_WIDTH-1:0]
dest_diag_level_bursts output [7:0] Diagnostics interface

Signals

Name Type Description
src_id_next reg [ID_WIDTH-1:0] * The burst memory is separated into 2**(ID_WIDTH-1) segments. Each segment can * hold up to BURST_LEN beats. The addresses that are used to access the memory * are split into two parts. The MSBs index the segment and the LSBs index a * beat in a specific segment. * * src_id and dest_id are used to index the segment of the burst memory on the * write and read side respectively. The IDs are 1 bit wider than the address of * the burst memory. So we can't use them directly as an index into the burst * memory. Since the IDs are gray counted we also can't just leave out the MSB * like with a binary counter. But XOR-ing the two MSBs of a gray counter gives * us a gray counter of 1 bit less. Use this to generate the segment index. * These addresses are captured in the src_id_reduced and dest_id_reduced * signals. * * src_beat_counter and dest_beat_counter are used to index the beat on the * write and read side respectively. They will be incremented for each beat that * is written/read. Note that the beat counters are not reset to 0 on the last * beat of a burst. This means the first beat of a burst might not be stored at * offset 0 in the segment memory. But this is OK since the beat counter * increments modulo the segment size and both the write and read side agree on * the order. */
src_id reg [ID_WIDTH-1:0]
src_id_reduced_msb reg
src_beat_counter reg [BURST_LEN_WIDTH_SRC-1:0]
dest_id_next reg [ID_WIDTH-1:0]
dest_id_reduced_msb_next reg
dest_id_reduced_msb reg
dest_id reg [ID_WIDTH-1:0]
dest_beat_counter reg [BURST_LEN_WIDTH_DEST-1:0]
dest_burst_len wire [BURST_LEN_WIDTH_DEST-1:0]
dest_valid reg
dest_mem_data_valid reg
dest_mem_data_last reg
dest_mem_data_strb reg [DATA_WIDTH_MEM_DEST/8-1:0]
burst_len_mem reg [BYTES_PER_BURST_WIDTH+1-1-DMA_LENGTH_ALIGN:0]
src_burst_len_data wire [BYTES_PER_BURST_WIDTH+1-1:0]
dest_burst_len_data reg [BYTES_PER_BURST_WIDTH+1-1:0]
src_beat wire
src_last_beat wire
src_dest_id wire [ID_WIDTH-1:0]
src_waddr wire [ADDRESS_WIDTH_SRC-1:0]
src_id_reduced wire [ID_WIDTH-2:0]
src_mem_data_valid wire
src_mem_data_last wire
src_mem_data wire [DATA_WIDTH_MEM_SRC-1:0]
src_mem_data_valid_bytes wire [BYTES_PER_BEAT_WIDTH_MEM_SRC-1:0]
src_mem_data_partial_burst wire
dest_beat wire
dest_last_beat wire
dest_last wire
dest_src_id wire [ID_WIDTH-1:0]
dest_raddr wire [ADDRESS_WIDTH_DEST-1:0]
dest_id_reduced_next wire [ID_WIDTH-2:0]
dest_id_next_inc wire [ID_WIDTH-1:0]
dest_id_reduced wire [ID_WIDTH-2:0]
dest_burst_valid wire
dest_burst_ready wire
dest_ready wire
dest_mem_data wire [DATA_WIDTH_MEM_DEST-1:0]
dest_mem_data_ready wire

Constants

Name Type Value Description
DATA_WIDTH_MEM DATA_W
MEM_RATIO DATA_WIDTH_SRC / DATA_WIDTH_DEST
BURST_LEN MAX_BYTES_PER_BURST A burst can have up to 256 beats */
BURST_LEN_WIDTH
AUX_FIFO_SIZE 2
MEM_RATIO_WIDTH MEM_RATIO == 2 ? 1 :
BURST_LEN_WIDTH_SRC BURST_LEN_WIDTH
BURST_LEN_WIDTH_DEST BURST_LEN_WIDTH
DATA_WIDTH_MEM_SRC DATA_WIDTH_MEM
DATA_WIDTH_MEM_DEST DATA_WIDTH_MEM
ADDRESS_WIDTH_SRC BURST_LEN_WIDTH_SRC + ID_WIDTH - 1
ADDRESS_WIDTH_DEST BURST_LEN_WIDTH_DEST + ID_WIDTH - 1
BYTES_PER_BEAT_WIDTH_MEM_SRC BYTES_PER_BURST_WIDTH - BURST_LEN_WIDTH_SRC
BYTES_PER_BEAT_WIDTH_DEST BYTES_PER_BURST_WIDTH - BURST_LEN_WIDTH_DEST

Processes

Type: always

Type: always

Type: always

Type: always

Type: always

Description

  • The data valid signal for the destination side is asserted if there are one * or more pending bursts. It is de-asserted if there are no more pending burst * and it is the last beat of the current burst */

Type: always

Description

  • The output register of the memory creates a extra clock cycle of latency on * the data path. We need to handle this more the handshaking signals. If data * is available in the memory it will be available one clock cycle later in the * output register. */

Type: always

Description

  • This clears dest_data_last after the last beat. Strictly speaking this is not * necessary if this followed AXI handshaking rules since dest_data_last would * be qualified by dest_data_valid and it is OK to retain the previous value of * dest_data_last when dest_data_valid is not asserted. But clearing the signal * here doesn't cost much and can simplify some of the more congested * combinatorical logic further up the pipeline since we can assume that * fifo_last == 1'b1 implies fifo_valid == 1'b1. */

Type: always

Type: always

Type: always

Type: always

Type: always

Type: always

Instantiations