Entity: axi_rd_wr_combiner

File: axi_rd_wr_combiner.v

Diagram

Description

In this HDL repository, there are many different and unique modules, consisting of various HDL (Verilog or VHDL) components. The individual modules are developed independently, and may be accompanied by separate and unique license terms.

The user should read each of these license terms, and understand the freedoms and responsibilities that he or she has by using this source/core.

This core is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.

Redistribution and use of source or resulting binaries, with or without modification of this file, are permitted under one of the following two license terms:

The GNU General Public License version 2 as published by the Free Software Foundation, which can be found in the top level directory of this repository (LICENSE_GPL2), and also online at: https://www.gnu.org/licenses/old-licenses/gpl-2.0.html

An ADI specific BSD license, which can be found in the top level directory of this repository (LICENSE_ADIBSD), and also on-line at: https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD This will allow to generate bit files and not release the source code, as long as it attaches to an ADI device.

Ports

Port name	Direction	Type	Description
clk	input
m_axi_awaddr	output	[31:0]	Master write address
m_axi_awlen	output	[ 3:0]
m_axi_awsize	output	[ 2:0]
m_axi_awburst	output	[ 1:0]
m_axi_awprot	output	[ 2:0]
m_axi_awcache	output	[ 3:0]
m_axi_awvalid	output
m_axi_awready	input
m_axi_wdata	output	[63:0]	Master write data
m_axi_wstrb	output	[ 7:0]
m_axi_wready	input
m_axi_wvalid	output
m_axi_wlast	output
m_axi_bvalid	input		Master write response
m_axi_bresp	input	[ 1:0]
m_axi_bready	output
m_axi_arvalid	output		Master read address
m_axi_araddr	output	[31:0]
m_axi_arlen	output	[ 3:0]
m_axi_arsize	output	[ 2:0]
m_axi_arburst	output	[ 1:0]
m_axi_arcache	output	[ 3:0]
m_axi_arprot	output	[ 2:0]
m_axi_arready	input
m_axi_rvalid	input		Master read response + data
m_axi_rresp	input	[ 1:0]
m_axi_rdata	input	[63:0]
m_axi_rlast	input
m_axi_rready	output
s_wr_axi_awaddr	input	[31:0]	Slave write address
s_wr_axi_awlen	input	[ 3:0]
s_wr_axi_awsize	input	[ 2:0]
s_wr_axi_awburst	input	[ 1:0]
s_wr_axi_awprot	input	[ 2:0]
s_wr_axi_awcache	input	[ 3:0]
s_wr_axi_awvalid	input
s_wr_axi_awready	output
s_wr_axi_wdata	input	[63:0]	Salve write data
s_wr_axi_wstrb	input	[ 7:0]
s_wr_axi_wready	output
s_wr_axi_wvalid	input
s_wr_axi_wlast	input
s_wr_axi_bvalid	output		Slave write response
s_wr_axi_bresp	output	[ 1:0]
s_wr_axi_bready	input
s_rd_axi_arvalid	input		Slave read address
s_rd_axi_araddr	input	[31:0]
s_rd_axi_arlen	input	[ 3:0]
s_rd_axi_arsize	input	[ 2:0]
s_rd_axi_arburst	input	[ 1:0]
s_rd_axi_arcache	input	[ 3:0]
s_rd_axi_arprot	input	[ 2:0]
s_rd_axi_arready	output
s_rd_axi_rvalid	output		Slave read response + data
s_rd_axi_rresp	output	[ 1:0]
s_rd_axi_rdata	output	[63:0]
s_rd_axi_rlast	output
s_rd_axi_rready	input