Entity: cic_interp
- File: cic_interp.v
Diagram
Description
Module: cic_interp Generated by MATLAB(R) 9.0 and the Filter Design HDL Coder 3.0.
Generated on: 2016-07-05 11:08:04
HDL Code Generation Options:
OptimizeForHDL: on EDAScriptGeneration: off AddPipelineRegisters: on Name: cic_interp AddRatePort: on InputDataType: numerictype(1,31,30) TargetLanguage: Verilog TestBenchName: cicinterpfilt_copy_tb TestBenchStimulus: step ramp chirp noise
GenerateHDLTestBench: off
HDL Implementation : Fully parallel
Filter Settings:
Discrete-Time FIR Multirate Filter (real)
Filter Structure : Cascaded Integrator-Comb Interpolator Interpolation Factor : 50000 Differential Delay : 1 Number of Sections : 6 Stable : Yes Linear Phase : No
Generics
| Generic name | Type | Value | Description |
|---|---|---|---|
| zeroconst | signed [35:0] | 36'h000000000 | sfix36_En30 |
Ports
| Port name | Direction | Type | Description |
|---|---|---|---|
| clk | input | ||
| clk_enable | input | ||
| reset | input | ||
| filter_in | input | signed [30:0] | sfix31_En30 |
| rate | input | [15:0] | ufix16 |
| load_rate | input | ||
| filter_out | output | signed [109:0] | sfix110_En30 |
| ce_out | output |
Signals
| Name | Type | Description |
|---|---|---|
| rate_unsigned | wire [15:0] | ufix16 |
| cur_count | reg [15:0] | ufix16 |
| phase_0 | wire | boolean |
| input_register | reg signed [30:0] | sfix31_En30 |
| section_in1 | wire [30:0] | sfix31_En30 |
| section_cast1 | wire [31:0] | sfix32_En30 |
| diff1 | reg signed [31:0] | sfix32_En30 |
| section_out1 | wire [31:0] | sfix32_En30 |
| sub_cast | wire [31:0] | sfix32_En30 |
| sub_cast_1 | wire [31:0] | sfix32_En30 |
| sub_temp | wire [32:0] | sfix33_En30 |
| cic_pipeline1 | reg signed [31:0] | sfix32_En30 |
| section_in2 | wire [31:0] | sfix32_En30 |
| section_cast2 | wire [32:0] | sfix33_En30 |
| diff2 | reg signed [32:0] | sfix33_En30 |
| section_out2 | wire [32:0] | sfix33_En30 |
| sub_cast_2 | wire [32:0] | sfix33_En30 |
| sub_cast_3 | wire [32:0] | sfix33_En30 |
| sub_temp_1 | wire [33:0] | sfix34_En30 |
| cic_pipeline2 | reg signed [32:0] | sfix33_En30 |
| section_in3 | wire [32:0] | sfix33_En30 |
| section_cast3 | wire [33:0] | sfix34_En30 |
| diff3 | reg signed [33:0] | sfix34_En30 |
| section_out3 | wire [33:0] | sfix34_En30 |
| sub_cast_4 | wire [33:0] | sfix34_En30 |
| sub_cast_5 | wire [33:0] | sfix34_En30 |
| sub_temp_2 | wire [34:0] | sfix35_En30 |
| cic_pipeline3 | reg signed [33:0] | sfix34_En30 |
| section_in4 | wire [33:0] | sfix34_En30 |
| section_cast4 | wire [34:0] | sfix35_En30 |
| diff4 | reg signed [34:0] | sfix35_En30 |
| section_out4 | wire [34:0] | sfix35_En30 |
| sub_cast_6 | wire [34:0] | sfix35_En30 |
| sub_cast_7 | wire [34:0] | sfix35_En30 |
| sub_temp_3 | wire [35:0] | sfix36_En30 |
| cic_pipeline4 | reg signed [34:0] | sfix35_En30 |
| section_in5 | wire [34:0] | sfix35_En30 |
| section_cast5 | wire [35:0] | sfix36_En30 |
| diff5 | reg signed [35:0] | sfix36_En30 |
| section_out5 | wire [35:0] | sfix36_En30 |
| sub_cast_8 | wire [35:0] | sfix36_En30 |
| sub_cast_9 | wire [35:0] | sfix36_En30 |
| sub_temp_4 | wire [36:0] | sfix37_En30 |
| cic_pipeline5 | reg signed [35:0] | sfix36_En30 |
| section_in6 | wire [35:0] | sfix36_En30 |
| diff6 | reg signed [35:0] | sfix36_En30 |
| section_out6 | wire [35:0] | sfix36_En30 |
| sub_cast_10 | wire [35:0] | sfix36_En30 |
| sub_cast_11 | wire [35:0] | sfix36_En30 |
| sub_temp_5 | wire [36:0] | sfix37_En30 |
| cic_pipeline6 | reg signed [35:0] | sfix36_En30 |
| upsampling | wire [35:0] | sfix36_En30 |
| section_in7 | wire [35:0] | sfix36_En30 |
| sum1 | wire [35:0] | sfix36_En30 |
| section_out7 | reg signed [35:0] | sfix36_En30 |
| add_cast | wire [35:0] | sfix36_En30 |
| add_cast_1 | wire [35:0] | sfix36_En30 |
| add_temp | wire [36:0] | sfix37_En30 |
| section_in8 | wire [35:0] | sfix36_En30 |
| section_cast8 | wire [50:0] | sfix51_En30 |
| sum2 | wire [50:0] | sfix51_En30 |
| section_out8 | reg signed [50:0] | sfix51_En30 |
| add_cast_2 | wire [50:0] | sfix51_En30 |
| add_cast_3 | wire [50:0] | sfix51_En30 |
| add_temp_1 | wire [51:0] | sfix52_En30 |
| section_in9 | wire [50:0] | sfix51_En30 |
| section_cast9 | wire [65:0] | sfix66_En30 |
| sum3 | wire [65:0] | sfix66_En30 |
| section_out9 | reg signed [65:0] | sfix66_En30 |
| add_cast_4 | wire [65:0] | sfix66_En30 |
| add_cast_5 | wire [65:0] | sfix66_En30 |
| add_temp_2 | wire [66:0] | sfix67_En30 |
| section_in10 | wire [65:0] | sfix66_En30 |
| section_cast10 | wire [79:0] | sfix80_En30 |
| sum4 | wire [79:0] | sfix80_En30 |
| section_out10 | reg signed [79:0] | sfix80_En30 |
| add_cast_6 | wire [79:0] | sfix80_En30 |
| add_cast_7 | wire [79:0] | sfix80_En30 |
| add_temp_3 | wire [80:0] | sfix81_En30 |
| section_in11 | wire [79:0] | sfix80_En30 |
| section_cast11 | wire [94:0] | sfix95_En30 |
| sum5 | wire [94:0] | sfix95_En30 |
| section_out11 | reg signed [94:0] | sfix95_En30 |
| add_cast_8 | wire [94:0] | sfix95_En30 |
| add_cast_9 | wire [94:0] | sfix95_En30 |
| add_temp_4 | wire [95:0] | sfix96_En30 |
| section_in12 | wire [94:0] | sfix95_En30 |
| section_cast12 | wire [109:0] | sfix110_En30 |
| sum6 | wire [109:0] | sfix110_En30 |
| section_out12 | reg signed [109:0] | sfix110_En30 |
| add_cast_10 | wire [109:0] | sfix110_En30 |
| add_cast_11 | wire [109:0] | sfix110_En30 |
| add_temp_5 | wire [110:0] | sfix111_En30 |
| bitgain | reg [6:0] | ufix7 |
| output_typeconvert | wire [109:0] | sfix110_En30 |
| muxinput_14 | wire [109:0] | sfix110_En16 |
| muxinput_34 | wire [109:0] | sfix110_E4 |
| muxinput_54 | wire [109:0] | sfix110_E24 |
| muxinput_74 | wire [109:0] | sfix110_E44 |
| muxinput_94 | wire [109:0] | sfix110_E64 |
| output_register | reg signed [109:0] | sfix110_En30 |
Processes
- ce_output: ( @ (posedge clk or posedge reset) )
Type: always
- input_reg_process: ( @ (posedge clk or posedge reset) )
Type: always
Description
------------------ Input Register ------------------
- comb_delay_section1: ( @ (posedge clk or posedge reset) )
Type: always
- cic_pipeline_process_section1: ( @ (posedge clk or posedge reset) )
Type: always
Description
comb_delay_section1
- comb_delay_section2: ( @ (posedge clk or posedge reset) )
Type: always
- cic_pipeline_process_section2: ( @ (posedge clk or posedge reset) )
Type: always
Description
comb_delay_section2
- comb_delay_section3: ( @ (posedge clk or posedge reset) )
Type: always
- cic_pipeline_process_section3: ( @ (posedge clk or posedge reset) )
Type: always
Description
comb_delay_section3
- comb_delay_section4: ( @ (posedge clk or posedge reset) )
Type: always
- cic_pipeline_process_section4: ( @ (posedge clk or posedge reset) )
Type: always
Description
comb_delay_section4
- comb_delay_section5: ( @ (posedge clk or posedge reset) )
Type: always
- cic_pipeline_process_section5: ( @ (posedge clk or posedge reset) )
Type: always
Description
comb_delay_section5
- comb_delay_section6: ( @ (posedge clk or posedge reset) )
Type: always
- cic_pipeline_process_section6: ( @ (posedge clk or posedge reset) )
Type: always
Description
comb_delay_section6
- integrator_delay_section7: ( @ (posedge clk or posedge reset) )
Type: always
- integrator_delay_section8: ( @ (posedge clk or posedge reset) )
Type: always
- integrator_delay_section9: ( @ (posedge clk or posedge reset) )
Type: always
- integrator_delay_section10: ( @ (posedge clk or posedge reset) )
Type: always
- integrator_delay_section11: ( @ (posedge clk or posedge reset) )
Type: always
- integrator_delay_section12: ( @ (posedge clk or posedge reset) )
Type: always
- unnamed: ( @(rate_unsigned) )
Type: always
Description
integrator_delay_section12
- output_reg_process: ( @ (posedge clk or posedge reset) )
Type: always
Description
------------------ Output Register ------------------