Entity: cn0363_dma_sequencer

Diagram

clk resetn [31:0] phase phase_valid [23:0] data data_valid [31:0] data_filtered data_filtered_valid [31:0] i_q i_q_valid [31:0] i_q_filtered i_q_filtered_valid dma_wr_overflow dma_wr_xfer_req [13:0] channel_enable phase_ready data_ready data_filtered_ready i_q_ready i_q_filtered_ready overflow [31:0] dma_wr_data dma_wr_en dma_wr_sync processing_resetn

Description

Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.

In this HDL repository, there are many different and unique modules, consisting of various HDL (Verilog or VHDL) components. The individual modules are developed independently, and may be accompanied by separate and unique license terms.

The user should read each of these license terms, and understand the freedoms and responsibilities that he or she has by using this source/core.

This core is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.

Redistribution and use of source or resulting binaries, with or without modification of this file, are permitted under one of the following two license terms:

  1. The GNU General Public License version 2 as published by the Free Software Foundation, which can be found in the top level directory of this repository (LICENSE_GPL2), and also online at: https://www.gnu.org/licenses/old-licenses/gpl-2.0.html

OR

  1. An ADI specific BSD license, which can be found in the top level directory of this repository (LICENSE_ADIBSD), and also on-line at: https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD This will allow to generate bit files and not release the source code, as long as it attaches to an ADI device.

Ports

Port name Direction Type Description
clk input
resetn input
phase input [31:0]
phase_valid input
phase_ready output
data input [23:0]
data_valid input
data_ready output
data_filtered input [31:0]
data_filtered_valid input
data_filtered_ready output
i_q input [31:0]
i_q_valid input
i_q_ready output
i_q_filtered input [31:0]
i_q_filtered_valid input
i_q_filtered_ready output
overflow output
dma_wr_data output [31:0]
dma_wr_en output
dma_wr_sync output
dma_wr_overflow input
dma_wr_xfer_req input
channel_enable input [13:0]
processing_resetn output

Signals

Name Type Description
count reg [3:0]

Processes

Type: always

Type: always

Type: always

Type: always

Type: always

Type: always

Type: always

Type: always

Type: always

State machines

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