Entity: data_offload_fsm
- File: data_offload_fsm.v
Diagram
Description
Copyright 2018 (c) Analog Devices, Inc. All rights reserved.
In this HDL repository, there are many different and unique modules, consisting of various HDL (Verilog or VHDL) components. The individual modules are developed independently, and may be accompanied by separate and unique license terms.
The user should read each of these license terms, and understand the freedoms and responsibilities that he or she has by using this source/core.
This core is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
Redistribution and use of source or resulting binaries, with or without modification of this file, are permitted under one of the following two license terms:
- The GNU General Public License version 2 as published by the Free Software Foundation, which can be found in the top level directory of this repository (LICENSE_GPL2), and also online at: https://www.gnu.org/licenses/old-licenses/gpl-2.0.html
OR
- An ADI specific BSD license, which can be found in the top level directory of this repository (LICENSE_ADIBSD), and also on-line at: https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD This will allow to generate bit files and not release the source code, as long as it attaches to an ADI device.
Generics
| Generic name | Type | Value | Description |
|---|---|---|---|
| TX_OR_RXN_PATH | 0 | ||
| WR_ADDRESS_WIDTH | 4 | ||
| WR_DATA_WIDTH | 128 | ||
| RD_ADDRESS_WIDTH | 4 | ||
| RD_DATA_WIDTH | 128 |
Ports
| Port name | Direction | Type | Description |
|---|---|---|---|
| wr_clk | input | write control interface | |
| wr_resetn_in | input | ||
| wr_resetn_out | output | ||
| wr_valid_in | input | ||
| wr_valid_out | output | ||
| wr_ready | output | ||
| wr_addr | output | [WR_ADDRESS_WIDTH-1:0] | |
| wr_last | input | ||
| wr_tkeep | input | [WR_DATA_WIDTH/8-1:0] | |
| rd_clk | input | read control interface | |
| rd_resetn_in | input | ||
| rd_resetn_out | output | ||
| rd_ready | input | ||
| rd_valid | output | reg | |
| rd_addr | output | [RD_ADDRESS_WIDTH-1:0] | |
| rd_last | output | ||
| rd_tkeep | output | [RD_DATA_WIDTH/8-1:0] | |
| rd_oneshot | input | 0 - CYCLIC; 1 - ONE_SHOT; | |
| init_req | input | Synchronization interface - synchronous to the device clock (ADC or DAC) | |
| init_ack | output | ||
| sync_config | input | [ 1:0] | |
| sync_external | input | ||
| sync_internal | input | ||
| wr_fsm_state | output | [ 1:0] | FSM debug |
| rd_fsm_state | output | [ 1:0] | |
| sample_count | output | [63:0] |
Signals
| Name | Type | Description |
|---|---|---|
| wr_last_addr | reg [WR_ADDRESS_WIDTH-1:0] | internal registers |
| wr_last_keep | reg [WR_DATA_WIDTH/8-1:0] | |
| rd_tkeep_last | reg [RD_DATA_WIDTH/8-1:0] | |
| rd_last_addr | reg [RD_ADDRESS_WIDTH-1:0] | |
| rd_isempty | reg | |
| rd_init_req_d | reg | |
| wr_init_req_d | reg | |
| wr_ready_d | reg | |
| wr_almost_full | wire | internal signals |
| wr_init_req_s | wire | |
| wr_init_req_pos_s | wire | |
| wr_init_ack_s | wire | |
| rd_isfull_s | wire | |
| wr_isempty_s | wire | |
| rd_empty_s | wire | |
| rd_wr_last_s | wire | |
| rd_init_req_s | wire | |
| rd_init_req_neg_s | wire | |
| rd_init_ack_s | wire | |
| rd_wr_last_addr_s | wire [WR_ADDRESS_WIDTH-1:0] | |
| rd_wr_last_tkeep_s | wire [WR_DATA_WIDTH/8-1:0] | |
| wr_sync_internal_s | wire | |
| rd_sync_internal_s | wire | |
| wr_sync_external_s | wire | |
| rd_sync_external_s | wire | |
| wr_oneshot | wire | |
| wr_fsm_state | reg [1:0] | |
| rd_fsm_state | reg [1:0] |
Constants
| Name | Type | Value | Description |
|---|---|---|---|
| WR_IDLE | 2'b00 | FSM states | |
| WR_SYNC | 2'b01 | ||
| WR_WRITE_TO_MEM | 2'b11 | ||
| WR_WAIT_TO_END | 2'b10 | ||
| RD_IDLE | 2'b00 | ||
| RD_SYNC | 2'b01 | ||
| RD_READ_FROM_MEM | 2'b11 | ||
| AUTOMATIC | 2'b00 | Synchronization options | |
| HARDWARE | 2'b01 | ||
| SOFTWARE | 2'b10 | ||
| LSB | WR_ADDRESS_WIDTH - RD_ADDRESS_WIDTH | helper parameters for last address, tkeep conversion | |
| POW2_LSB | 1 << LSB |
Processes
- unnamed: ( @(posedge wr_clk) )
Type: always
Description
Mealy state machine for write control
- unnamed: ( @(posedge wr_clk) )
Type: always
Description
the initialization interface (init_req) is edge sensitive
- unnamed: ( @(posedge wr_clk) )
Type: always
Description
write address generation
- unnamed: ( @(posedge wr_clk) )
Type: always
Description
reset the storage unit's FMS before each transfer
- unnamed: ( @(posedge wr_clk) )
Type: always
- unnamed: ( @(posedge wr_clk) )
Type: always
- unnamed: ( @(posedge wr_clk) )
Type: always
- unnamed: ( @(posedge wr_clk) )
Type: always
Description
sample counter for debug purposes, the value of the counter resets at every new incoming request
- unnamed: ( @(posedge rd_clk) )
Type: always
Description
Mealy state machine for read control
- unnamed: ( @(posedge rd_clk) )
Type: always
Description
the initialization interface (init_req) is edge sensitive TODO: This should be redefined! Will work only of init_req is active during the whole DMA transfer (use xfer_req for driving init_req)
- unnamed: ( @(posedge rd_clk) )
Type: always
Description
Reset the storage unit's FSM before each transfer
- unnamed: ( @(posedge rd_clk) )
Type: always
Description
read address generation
- unnamed: ( @(posedge rd_clk) )
Type: always
- unnamed: ( @(posedge rd_clk) )
Type: always
- unnamed: ( @(posedge rd_clk) )
Type: always
Instantiations
- i_wr_empty_sync: sync_event
Description
CDC circuits
- i_rd_full_sync: sync_event
- i_rd_wr_last_sync: sync_event
- i_wr_oneshot_sync: sync_bits
- i_rd_init_req_sync: sync_bits
- i_wr_init_req_sync: sync_bits
- i_rd_last_address: sync_bits
Description
convert write address and last/keep to read address and last/keep
- i_rd_last_keep: sync_bits
- i_sync_wr_sync: sync_bits
- i_sync_rd_sync: sync_bits
State machines
- Mealy state machine for write control
- Mealy state machine for read control