Entity: util_axis_resize

Diagram

MASTER_DATA_WIDTH SLAVE_DATA_WIDTH BIG_ENDIAN clk resetn s_valid [SLAVE_DATA_WIDTH-1:0] s_data m_ready s_ready m_valid [MASTER_DATA_WIDTH-1:0] m_data

Description

Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.

In this HDL repository, there are many different and unique modules, consisting of various HDL (Verilog or VHDL) components. The individual modules are developed independently, and may be accompanied by separate and unique license terms.

The user should read each of these license terms, and understand the freedoms and responsibilities that he or she has by using this source/core.

This core is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.

Redistribution and use of source or resulting binaries, with or without modification of this file, are permitted under one of the following two license terms:

  1. The GNU General Public License version 2 as published by the Free Software Foundation, which can be found in the top level directory of this repository (LICENSE_GPL2), and also online at: https://www.gnu.org/licenses/old-licenses/gpl-2.0.html

OR

  1. An ADI specific BSD license, which can be found in the top level directory of this repository (LICENSE_ADIBSD), and also on-line at: https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD This will allow to generate bit files and not release the source code, as long as it attaches to an ADI device.

Generics

Generic name Type Value Description
MASTER_DATA_WIDTH 64
SLAVE_DATA_WIDTH 64
BIG_ENDIAN 0

Ports

Port name Direction Type Description
clk input
resetn input
s_valid input
s_ready output
s_data input [SLAVE_DATA_WIDTH-1:0]
m_valid output
m_ready input
m_data output [MASTER_DATA_WIDTH-1:0]

Constants

Name Type Value Description
RATIO MASTER_DATA_WIDTH / SLAVE_DATA_WIDTH

Functions