Entity: asic_clkicgand
- File: asic_clkicgand.v
Diagram
Description
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Function: Integrated "And" Clock Gating Cell (And)
Copyright: OH Project Authors. ALl rights Reserved.
License: MIT (see LICENSE file in OH repository)
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Generics
| Generic name | Type | Value | Description |
|---|---|---|---|
| PROP | "DEFAULT" |
Ports
| Port name | Direction | Type | Description |
|---|---|---|---|
| clk | input | clock input | |
| te | input | test enable | |
| en | input | enable (from positive edge FF) | |
| eclk | output | enabled clock output |
Signals
| Name | Type | Description |
|---|---|---|
| en_stable | reg |
Processes
- unnamed: ( @ (clk or en or te) )
Type: always