Entity: axi_etrace

Diagram

AW DW PW ID S_IDW M_IDW m_axi_aclk m_axi_aresetn m_axi_awready m_axi_wready [M_IDW-1:0] m_axi_bid [1 : 0] m_axi_bresp m_axi_bvalid m_axi_arready [M_IDW-1:0] m_axi_rid [63 : 0] m_axi_rdata [1 : 0] m_axi_rresp m_axi_rlast m_axi_rvalid s_axi_aclk s_axi_aresetn [S_IDW-1:0] s_axi_arid [31:0] s_axi_araddr [1:0] s_axi_arburst [3:0] s_axi_arcache s_axi_arlock [7:0] s_axi_arlen [2:0] s_axi_arprot [3:0] s_axi_arqos [2:0] s_axi_arsize s_axi_arvalid [S_IDW-1:0] s_axi_awid [31:0] s_axi_awaddr [1:0] s_axi_awburst [3:0] s_axi_awcache s_axi_awlock [7:0] s_axi_awlen [2:0] s_axi_awprot [3:0] s_axi_awqos [2:0] s_axi_awsize s_axi_awvalid s_axi_bready s_axi_rready [S_IDW-1:0] s_axi_wid [31:0] s_axi_wdata s_axi_wlast [3:0] s_axi_wstrb s_axi_wvalid cfg_access_in [PW-1:0] cfg_packet_in emesh_wait rd_access [PW-1:0] rd_packet rxrr_access [PW-1:0] rxrr_packet rxwr_access [PW-1:0] rxwr_packet trace_clk trace_trigger [VW-1:0] trace_vector txrd_wait txwr_wait wr_access [PW-1:0] wr_packet [M_IDW-1:0] m_axi_awid [31 : 0] m_axi_awaddr [7 : 0] m_axi_awlen [2 : 0] m_axi_awsize [1 : 0] m_axi_awburst m_axi_awlock [3 : 0] m_axi_awcache [2 : 0] m_axi_awprot [3 : 0] m_axi_awqos m_axi_awvalid [M_IDW-1:0] m_axi_wid [63 : 0] m_axi_wdata [7 : 0] m_axi_wstrb m_axi_wlast m_axi_wvalid m_axi_bready [M_IDW-1:0] m_axi_arid [31 : 0] m_axi_araddr [7 : 0] m_axi_arlen [2 : 0] m_axi_arsize [1 : 0] m_axi_arburst m_axi_arlock [3 : 0] m_axi_arcache [2 : 0] m_axi_arprot [3 : 0] m_axi_arqos m_axi_arvalid m_axi_rready s_axi_arready s_axi_awready [S_IDW-1:0] s_axi_bid [1:0] s_axi_bresp s_axi_bvalid [S_IDW-1:0] s_axi_rid [31:0] s_axi_rdata s_axi_rlast [1:0] s_axi_rresp s_axi_rvalid s_axi_wready cfg_access_out [PW-1:0] cfg_packet_out data_access_out [PW-1:0] data_packet_out emesh_access [PW-1:0] emesh_packet rd_wait rxrr_wait rxwr_wait txrd_access [PW-1:0] txrd_packet txwr_access [PW-1:0] txwr_packet wr_wait

Generics

Generic name Type Value Description
AW 32
DW 32
PW 104 packet width
ID 12'h810
S_IDW 12 ID width for S_AXI
M_IDW 6 ID width for M_AXI

Ports

Port name Direction Type Description
m_axi_aclk input ########################AXI MASTER INTERFACE ######################## clk+reset
m_axi_aresetn input global reset singal.
m_axi_awid output [M_IDW-1:0] write address ID
m_axi_awaddr output [31 : 0] master interface write address
m_axi_awlen output [7 : 0] burst length.
m_axi_awsize output [2 : 0] burst size.
m_axi_awburst output [1 : 0] burst type.
m_axi_awlock output lock type
m_axi_awcache output [3 : 0] memory type.
m_axi_awprot output [2 : 0] protection type.
m_axi_awqos output [3 : 0] quality of service
m_axi_awvalid output write address valid
m_axi_awready input write address ready
m_axi_wid output [M_IDW-1:0] Write data channel
m_axi_wdata output [63 : 0] master interface write data.
m_axi_wstrb output [7 : 0] byte write strobes
m_axi_wlast output last transfer in a write burst.
m_axi_wvalid output indicates data is ready to go
m_axi_wready input slave is ready for data
m_axi_bid input [M_IDW-1:0] Write response channel
m_axi_bresp input [1 : 0] status of the write transaction.
m_axi_bvalid input valid write response
m_axi_bready output master can accept write response.
m_axi_arid output [M_IDW-1:0] read address ID
m_axi_araddr output [31 : 0] initial address of a read burst
m_axi_arlen output [7 : 0] burst length
m_axi_arsize output [2 : 0] burst size
m_axi_arburst output [1 : 0] burst type
m_axi_arlock output lock type
m_axi_arcache output [3 : 0] memory type
m_axi_arprot output [2 : 0] protection type
m_axi_arqos output [3 : 0] --
m_axi_arvalid output read address and control is valid
m_axi_arready input slave is ready to accept an address
m_axi_rid input [M_IDW-1:0] Read data channel
m_axi_rdata input [63 : 0] master read data
m_axi_rresp input [1 : 0] status of the read transfer
m_axi_rlast input signals last transfer in a read burst
m_axi_rvalid input signaling the required read data
m_axi_rready output master can accept the readback data
s_axi_aclk input ########################AXI SLAVE INTERFACE ######################## clk+reset
s_axi_aresetn input
s_axi_arid input [S_IDW-1:0] write address ID
s_axi_araddr input [31:0]
s_axi_arburst input [1:0]
s_axi_arcache input [3:0]
s_axi_arlock input
s_axi_arlen input [7:0]
s_axi_arprot input [2:0]
s_axi_arqos input [3:0]
s_axi_arready output
s_axi_arsize input [2:0]
s_axi_arvalid input
s_axi_awid input [S_IDW-1:0] write address ID
s_axi_awaddr input [31:0]
s_axi_awburst input [1:0]
s_axi_awcache input [3:0]
s_axi_awlock input
s_axi_awlen input [7:0]
s_axi_awprot input [2:0]
s_axi_awqos input [3:0]
s_axi_awsize input [2:0]
s_axi_awvalid input
s_axi_awready output
s_axi_bid output [S_IDW-1:0] write address ID
s_axi_bresp output [1:0]
s_axi_bvalid output
s_axi_bready input
s_axi_rid output [S_IDW-1:0] write address ID
s_axi_rdata output [31:0]
s_axi_rlast output
s_axi_rresp output [1:0]
s_axi_rvalid output
s_axi_rready input
s_axi_wid input [S_IDW-1:0] write address ID
s_axi_wdata input [31:0]
s_axi_wlast input
s_axi_wstrb input [3:0]
s_axi_wvalid input
s_axi_wready output
cfg_access_in input To etrace of etrace.v
cfg_packet_in input [PW-1:0] To etrace of etrace.v
emesh_wait input To emesh_mux of emesh_mux.v
rd_access input To emesh_mux of emesh_mux.v
rd_packet input [PW-1:0] To emesh_mux of emesh_mux.v
rxrr_access input To esaxi of esaxi.v
rxrr_packet input [PW-1:0] To esaxi of esaxi.v
rxwr_access input To emaxi of emaxi.v
rxwr_packet input [PW-1:0] To emaxi of emaxi.v
trace_clk input To etrace of etrace.v
trace_trigger input To etrace of etrace.v
trace_vector input [VW-1:0] To etrace of etrace.v
txrd_wait input To esaxi of esaxi.v
txwr_wait input To esaxi of esaxi.v
wr_access input To emesh_mux of emesh_mux.v
wr_packet input [PW-1:0] To emesh_mux of emesh_mux.v
cfg_access_out output From etrace of etrace.v
cfg_packet_out output [PW-1:0] From etrace of etrace.v
data_access_out output From etrace of etrace.v
data_packet_out output [PW-1:0] From etrace of etrace.v
emesh_access output From emesh_mux of emesh_mux.v
emesh_packet output [PW-1:0] From emesh_mux of emesh_mux.v
rd_wait output From emesh_mux of emesh_mux.v
rxrr_wait output From esaxi of esaxi.v
rxwr_wait output From emaxi of emaxi.v
txrd_access output From esaxi of esaxi.v
txrd_packet output [PW-1:0] From esaxi of esaxi.v
txwr_access output From esaxi of esaxi.v
txwr_packet output [PW-1:0] From esaxi of esaxi.v
wr_wait output From emesh_mux of emesh_mux.v