Entity: axi_spi

Diagram

AW PW ID S_IDW sys_nreset sys_clk [31:0] s_axi_araddr [1:0] s_axi_arburst [3:0] s_axi_arcache s_axi_aresetn [S_IDW-1:0] s_axi_arid [7:0] s_axi_arlen s_axi_arlock [2:0] s_axi_arprot [3:0] s_axi_arqos [2:0] s_axi_arsize s_axi_arvalid [31:0] s_axi_awaddr [1:0] s_axi_awburst [3:0] s_axi_awcache [S_IDW-1:0] s_axi_awid [7:0] s_axi_awlen s_axi_awlock [2:0] s_axi_awprot [3:0] s_axi_awqos [2:0] s_axi_awsize s_axi_awvalid s_axi_bready s_axi_rready [31:0] s_axi_wdata [S_IDW-1:0] s_axi_wid s_axi_wlast [3:0] s_axi_wstrb s_axi_wvalid spi_m_miso spi_s_mosi spi_s_sclk spi_s_ss s_axi_arready s_axi_awready [S_IDW-1:0] s_axi_bid [1:0] s_axi_bresp s_axi_bvalid [31:0] s_axi_rdata [S_IDW-1:0] s_axi_rid s_axi_rlast [1:0] s_axi_rresp s_axi_rvalid s_axi_wready spi_irq spi_m_mosi spi_m_sclk spi_m_ss spi_s_miso

Description

#############################################################################

Purpose: AXI spi module

#############################################################################

Author: Ola Jeppsson

SPDX-License-Identifier: MIT

#############################################################################

Generics

Generic name Type Value Description
AW 32 address width
PW 2*AW+40 packet width
ID 12'h810 addr[31:20] id
S_IDW 12 ID width for S_AXI

Ports

Port name Direction Type Description
sys_nreset input active low async reset
sys_clk input system clock for AXI
s_axi_araddr input [31:0] To esaxi of esaxi.v
s_axi_arburst input [1:0] To esaxi of esaxi.v
s_axi_arcache input [3:0] To esaxi of esaxi.v
s_axi_aresetn input To esaxi of esaxi.v
s_axi_arid input [S_IDW-1:0] To esaxi of esaxi.v
s_axi_arlen input [7:0] To esaxi of esaxi.v
s_axi_arlock input To esaxi of esaxi.v
s_axi_arprot input [2:0] To esaxi of esaxi.v
s_axi_arqos input [3:0] To esaxi of esaxi.v
s_axi_arsize input [2:0] To esaxi of esaxi.v
s_axi_arvalid input To esaxi of esaxi.v
s_axi_awaddr input [31:0] To esaxi of esaxi.v
s_axi_awburst input [1:0] To esaxi of esaxi.v
s_axi_awcache input [3:0] To esaxi of esaxi.v
s_axi_awid input [S_IDW-1:0] To esaxi of esaxi.v
s_axi_awlen input [7:0] To esaxi of esaxi.v
s_axi_awlock input To esaxi of esaxi.v
s_axi_awprot input [2:0] To esaxi of esaxi.v
s_axi_awqos input [3:0] To esaxi of esaxi.v
s_axi_awsize input [2:0] To esaxi of esaxi.v
s_axi_awvalid input To esaxi of esaxi.v
s_axi_bready input To esaxi of esaxi.v
s_axi_rready input To esaxi of esaxi.v
s_axi_wdata input [31:0] To esaxi of esaxi.v
s_axi_wid input [S_IDW-1:0] To esaxi of esaxi.v
s_axi_wlast input To esaxi of esaxi.v
s_axi_wstrb input [3:0] To esaxi of esaxi.v
s_axi_wvalid input To esaxi of esaxi.v
spi_m_miso input To spi of spi.v
spi_s_mosi input To spi of spi.v
spi_s_sclk input To spi of spi.v
spi_s_ss input To spi of spi.v
s_axi_arready output From esaxi of esaxi.v
s_axi_awready output From esaxi of esaxi.v
s_axi_bid output [S_IDW-1:0] From esaxi of esaxi.v
s_axi_bresp output [1:0] From esaxi of esaxi.v
s_axi_bvalid output From esaxi of esaxi.v
s_axi_rdata output [31:0] From esaxi of esaxi.v
s_axi_rid output [S_IDW-1:0] From esaxi of esaxi.v
s_axi_rlast output From esaxi of esaxi.v
s_axi_rresp output [1:0] From esaxi of esaxi.v
s_axi_rvalid output From esaxi of esaxi.v
s_axi_wready output From esaxi of esaxi.v
spi_irq output From spi of spi.v
spi_m_mosi output From spi of spi.v
spi_m_sclk output From spi of spi.v
spi_m_ss output From spi of spi.v
spi_s_miso output From spi of spi.v

Signals

Name Type Description
s_wr_access wire ############################ HOST GENERATERD ############################ Slave Write
s_wr_packet wire [PW-1:0]
s_wr_wait wire
s_rd_access wire Slave Read Request
s_rd_packet wire [PW-1:0]
s_rd_wait wire
s_rr_access wire Slave Read Response
s_rr_packet wire [PW-1:0]
s_rr_wait wire
spi_wait_out wire End of automatics AUTOWIRE/ AUTOREG/
spi_access_out wire
spi_packet_out wire [PW-1:0]
spi_access_in wire
spi_packet_in wire [PW-1:0]
spi_wait_in wire