Entity: axislave_stub

Diagram

S_IDW s_axi_aclk s_axi_aresetn [S_IDW-1:0] s_axi_arid [31:0] s_axi_araddr [1:0] s_axi_arburst [3:0] s_axi_arcache s_axi_arlock [7:0] s_axi_arlen [2:0] s_axi_arprot [3:0] s_axi_arqos [2:0] s_axi_arsize s_axi_arvalid [S_IDW-1:0] s_axi_awid [31:0] s_axi_awaddr [1:0] s_axi_awburst [3:0] s_axi_awcache s_axi_awlock [7:0] s_axi_awlen [2:0] s_axi_awprot [3:0] s_axi_awqos [2:0] s_axi_awsize s_axi_awvalid s_axi_bready s_axi_rready [S_IDW-1:0] s_axi_wid [31:0] s_axi_wdata s_axi_wlast [3:0] s_axi_wstrb s_axi_wvalid s_axi_arready s_axi_awready [S_IDW-1:0] s_axi_bid [1:0] s_axi_bresp s_axi_bvalid [S_IDW-1:0] s_axi_rid [31:0] s_axi_rdata s_axi_rlast [1:0] s_axi_rresp s_axi_rvalid s_axi_wready

Generics

Generic name Type Value Description
S_IDW 12

Ports

Port name Direction Type Description
s_axi_aclk input /AXI slave interface / */ Clock and reset
s_axi_aresetn input
s_axi_arid input [S_IDW-1:0] write address ID
s_axi_araddr input [31:0]
s_axi_arburst input [1:0]
s_axi_arcache input [3:0]
s_axi_arlock input
s_axi_arlen input [7:0]
s_axi_arprot input [2:0]
s_axi_arqos input [3:0]
s_axi_arready output
s_axi_arsize input [2:0]
s_axi_arvalid input
s_axi_awid input [S_IDW-1:0] write address ID
s_axi_awaddr input [31:0]
s_axi_awburst input [1:0]
s_axi_awcache input [3:0]
s_axi_awlock input
s_axi_awlen input [7:0]
s_axi_awprot input [2:0]
s_axi_awqos input [3:0]
s_axi_awsize input [2:0]
s_axi_awvalid input
s_axi_awready output
s_axi_bid output [S_IDW-1:0] write address ID
s_axi_bresp output [1:0]
s_axi_bvalid output
s_axi_bready input
s_axi_rid output [S_IDW-1:0] write address ID
s_axi_rdata output [31:0]
s_axi_rlast output
s_axi_rresp output [1:0]
s_axi_rvalid output
s_axi_rready input
s_axi_wid input [S_IDW-1:0] write address ID
s_axi_wdata input [31:0]
s_axi_wlast input
s_axi_wstrb input [3:0]
s_axi_wvalid input
s_axi_wready output