Entity: edma_ctrl

• File: edma_ctrl.v

Diagram

Description

Generics

Generic name	Type	Value	Description
AW		32	address width
PW		2*AW+40	fetch packet width
ID		4'b0000	group id for DMA regs [10:8]

Ports

Port name	Direction	Type	Description
clk	input		main clock
nreset	input		async active low reset
dma_en	input		dma is enabled
chainmode	input		chainmode configuration
manualmode	input		descriptor fetch
mastermode	input		dma configured in mastermode
count	input	[31:0]	current transfer count
curr_descr	input	[15:0]
next_descr	input	[15:0]
fetch_access	output		fetch descriptor
fetch_packet	output	[PW-1:0]	fetch packet
reg_wait_in	input		register access wait
access_in	input		slave access
wait_in	input		master/slave transfer stall
dma_state	output	[3:0]	state of dma
update	output		update registers
update2d	output		dma currently in outerloop (2D)
master_active	output		master is active

Signals

Name	Type	Description
dma_state	reg [3:0]	########################################################################### # BODY ###########################################################################
descr	wire [15:0]
fetch_addr	wire [15:0]
srcaddr_out	wire [AW-1:0]
reg_addr	wire [4:0]
dma_error	wire
incount_zero	wire
outcount_zero	wire

Processes

• unnamed: ( @ (posedge clk or negedge nreset) )

Instantiations

• mux3d: oh_mux3

• mux3s: oh_mux3

State machines