Entity: etx_protocol

• File: etx_protocol.v

Diagram

Description

Generics

Generic name	Type	Value	Description
PW		104
AW		32
DW		32
ID		12'h000

Ports

Port name	Direction	Type	Description
nreset	input		Clock/reset
clk	input
etx_access	input		System side
etx_packet	input	[PW-1:0]
etx_rd_wait	output		Pushback signals
etx_wr_wait	output
etx_wait	output
tx_enable	input		transmit enable
burst_enable	input		Enables bursting
gpio_data	input	[8:0]	TODO
gpio_enable	input		TODO
tx_burst	output		for TXSTATUS
tx_access	output		for TXMON
ctrlmode_bypass	input		ctrlmode for rd/wr transactions
ctrlmode	input	[3:0]
tx_data_slow	output	[63:0]	Interface to IO
tx_frame_slow	output	[3:0]
tx_rd_wait	input
tx_wr_wait	input

Signals

Name	Type	Description
tx_state	reg [2:0]	################################################################ # Local regs & wires ################################################################
tx_packet	reg [PW-1:0]
tx_burst_reg	reg
etx_datamode	wire [1:0]
etx_ctrlmode	wire [4:0]
etx_dstaddr	wire [AW-1:0]
etx_data	wire [DW-1:0]
tx_datamode	wire [1:0]
tx_ctrlmode	wire [4:0]
tx_dstaddr	wire [AW-1:0]
tx_data	wire [DW-1:0]
tx_srcaddr	wire [AW-1:0]
ctrlmode_mux	wire [3:0]
tx_cycle1	wire [63:0]	####################################### # Wait propagation circuit backwards ########################################
tx_cycle2	wire [63:0]

Processes

• unnamed: ( @ (posedge clk) )

• unnamed: ( @ (posedge clk) )

• unnamed: ( @ (posedge clk) )

State machines