Entity: spi_master_io
- File: spi_master_io.v
Diagram
Description
#############################################################################
Purpose: SPI master IO state-machine
#############################################################################
Author: Andreas Olofsson
License: MIT (see LICENSE file in OH! repository) #
#############################################################################
Ports
| Port name | Direction | Type | Description |
|---|---|---|---|
| clk | input | core clock | |
| nreset | input | async active low reset | |
| cpol | input | cpol | |
| cpha | input | cpha | |
| lsbfirst | input | send lsbfirst | |
| manual_mode | input | sets automatic ss mode | |
| send_data | input | controls ss in manual ss mode | |
| clkdiv_reg | input | [7:0] | baudrate |
| spi_state | output | [2:0] | current spi tx state |
| fifo_dout | input | [7:0] | data payload |
| fifo_empty | input | ||
| fifo_read | output | read new byte | |
| rx_data | output | [63:0] | rx data |
| rx_access | output | transfer done | |
| sclk | output | spi clock | |
| mosi | output | slave input | |
| ss | output | slave select | |
| miso | input | slave output |
Signals
| Name | Type | Description |
|---|---|---|
| fifo_empty_reg | reg | ############### # LOCAL WIRES ############### |
| load_byte | reg | |
| ss_reg | reg | |
| data_out | wire [7:0] | |
| clkphase0 | wire [15:0] | |
| period_match | wire | |
| phase_match | wire | |
| clkout | wire | |
| clkchange | wire | |
| data_done | wire | |
| spi_wait | wire | |
| shift | wire | |
| spi_active | wire | |
| tx_shift | wire | |
| rx_shift | wire |
Processes
- unnamed: ( @ (posedge clk or negedge nreset) )
Type: always
- unnamed: ( @ (posedge clk) )
Type: always
Description
load is the result of the fifo_read
- unnamed: ( @ (posedge clk or negedge nreset) )
Type: always
Description
################################# # DRIVE OUTPUT CLOCK #################################
- unnamed: ( @ (posedge clk or negedge nreset) )
Type: always
Description
shift data generate access pulse at rise of ss
Instantiations
- oh_clockdiv: oh_clockdiv
- par2ser: oh_par2ser
- ser2par: oh_ser2par
State machines
undefined