Entity: spi_slave_io
- File: spi_slave_io.v
Diagram
Description
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Purpose: SPI slave IO state-machine
NOTE: only cpol=0, cpha=0 supported for now!!
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Author: Andreas Olofsson
License: MIT (see LICENSE file in OH! repository) #
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Generics
| Generic name | Type | Value | Description |
|---|---|---|---|
| PW | 104 | packet width |
Ports
| Port name | Direction | Type | Description |
|---|---|---|---|
| sclk | input | slave clock | |
| mosi | input | slave input | |
| ss | input | slave select | |
| miso | output | slave output | |
| spi_en | input | spi enable | |
| cpol | input | cpol | |
| cpha | input | cpha | |
| lsbfirst | input | lsbfirst | |
| spi_clk | output | spi clock for regfile | |
| spi_write | output | regfile write | |
| spi_addr | output | [5:0] | regfile addres |
| spi_wdata | output | [7:0] | data for regfile |
| spi_rdata | input | [7:0] | data for regfile |
| clk | input | core clock | |
| nreset | input | async active low reset | |
| access_out | output | read or write core command | |
| packet_out | output | [PW-1:0] | packet |
| wait_in | input | temporary pushback |
Signals
| Name | Type | Description |
|---|---|---|
| access_reg | reg | ############### # LOCAL WIRES ############### |
| spi_state | reg [1:0] | |
| bit_count | reg [7:0] | |
| command_reg | reg [7:0] | |
| fetch_command | reg | |
| rx_data | wire [7:0] | |
| tx_data | wire [63:0] | |
| rx_shift | wire | |
| tx_load | wire | |
| tx_wait | wire | |
| ss_sync | wire | |
| ss_pulse | wire | |
| spi_fetch | wire | |
| byte_done | wire | |
| shift | wire | |
| rx_clk | wire | |
| tx_clk | wire | |
| next_byte | wire |
Processes
- unnamed: ( @ (posedge sclk or posedge ss) )
Type: always
Description
state machine
- unnamed: ( @ (posedge sclk or posedge ss) )
Type: always
Description
case (spi_state[1:0]) bit counter
- unnamed: ( @ (posedge sclk or negedge nreset) )
Type: always
Description
command/address register auto increment for every byte
- unnamed: ( @ (posedge clk or negedge nreset) )
Type: always
Description
pipeleining and holding pulse if there is wait
Instantiations
- rx_ser2par: oh_ser2par
Description
#################################
SPI RX SHIFT REGISTER
#################################
- tx_par2ser: oh_par2ser
Description
#################################
TX SHIFT REGISTER
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- dsync: oh_dsync
Description
rx_shift
sync the ss to free running clk
- r2p: oh_rise2pulse
Description
create single cycle pulse
State machines
- state machine
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