Entity: stimulus
- File: stimulus.v
Diagram
Description
A stimulus file provides inputs signals to the design under test (DUT). This stimulus module is designed to be compatible with verilog simulators, emulators, and FPGA prototyping. This is akin to a simple test vector generator No looping supported!
Memory format: b0 = valid, b1-7 = wait time b8-bxxx = packet
Test Process:
- Zero out memory (or write program)
- Set go signal
Generics
| Generic name | Type | Value | Description |
|---|---|---|---|
| DW | 32 | Memory width=DW+ | |
| MAW | 15 | Memory address width | |
| HEXFILE | "NONE" | Name of hex file |
Ports
| Port name | Direction | Type | Description |
|---|---|---|---|
| nreset | input | Asynchronous Stimulus Reset | |
| ext_start | input | Start driving stimulus | |
| use_timestamps | input | b1-7 used for timestamps | |
| ignore_valid | input | b0 valid bit ignored | |
| ext_clk | input | External clock for write path | |
| ext_access | input | Valid packet for memory | |
| ext_packet | input | [DW-1:0] | Packet for memory |
| dut_clk | input | DUT side clock | |
| dut_wait | input | DUT stall signal | |
| stim_access | output | Access signal | |
| stim_packet | output | [DW-1:0] | Packet |
| stim_done | output | Stimulus program done |
Signals
| Name | Type | Description |
|---|---|---|
| ram | reg [DW-1:0] | Registers |
| rd_state | reg [1:0] | |
| wr_addr | reg [MAW-1:0] | |
| rd_addr | reg [MAW-1:0] | |
| memhfile | reg [255:0] | |
| sync_pipe | reg [1:0] | |
| rd_delay | reg [6:0] | |
| stim_packet | reg [DW-1:0] | |
| stim_read | reg |
Constants
| Name | Type | Value | Description |
|---|---|---|---|
| MD | 1<<MAW | Memory depth |
Processes
- unnamed: ( @ (posedge ext_clk or negedge nreset) )
Type: always
Description
################################# Write port state machine #################################
- unnamed: ( @ (posedge dut_clk or negedge nreset) )
Type: always
Description
Synchronize ext_start to dut_clk domain
- unnamed: ( @ (posedge dut_clk or negedge nreset) )
Type: always
- unnamed: ( @(posedge ext_clk) )
Type: always
Description
################################# RAM ################################# write port
- unnamed: ( @ (posedge dut_clk) )
Type: always
Description
read port
State machines
undefined