Package: adc_ctrl_reg_pkg

Description

Copyright lowRISC contributors.
Licensed under the Apache License, Version 2.0, see LICENSE for details.
SPDX-License-Identifier: Apache-2.0

Register Package auto-generated by reggen containing data structure

Constants

Name Type Value Description
NumAdcFilter int 8
NumAdcChannel int 2
NumAlerts int 1
BlockAw int 7 Address widths within the block
BlockAw logic [BlockAw-1:0] undefined Register offsets
BlockAw logic [BlockAw-1:0] 4
BlockAw logic [BlockAw-1:0] 8
BlockAw logic [BlockAw-1:0] c
BlockAw logic [BlockAw-1:0] 10
BlockAw logic [BlockAw-1:0] 14
BlockAw logic [BlockAw-1:0] 18
BlockAw logic [BlockAw-1:0] c
BlockAw logic [BlockAw-1:0] 20
BlockAw logic [BlockAw-1:0] 24
BlockAw logic [BlockAw-1:0] 28
BlockAw logic [BlockAw-1:0] c
BlockAw logic [BlockAw-1:0] 30
BlockAw logic [BlockAw-1:0] 34
BlockAw logic [BlockAw-1:0] 38
BlockAw logic [BlockAw-1:0] c
BlockAw logic [BlockAw-1:0] 40
BlockAw logic [BlockAw-1:0] 44
BlockAw logic [BlockAw-1:0] 48
BlockAw logic [BlockAw-1:0] c
BlockAw logic [BlockAw-1:0] 50
BlockAw logic [BlockAw-1:0] 54
BlockAw logic [BlockAw-1:0] 58
BlockAw logic [BlockAw-1:0] c
BlockAw logic [BlockAw-1:0] 60
BlockAw logic [BlockAw-1:0] 64
BlockAw logic [BlockAw-1:0] 68
BlockAw logic [BlockAw-1:0] c
BlockAw logic [BlockAw-1:0] 70
BlockAw logic [BlockAw-1:0] 74
BlockAw logic [BlockAw-1:0] 78
ADC_CTRL_INTR_TEST_RESVAL logic [0:0] undefined Reset values for hwext registers and their fields
ADC_CTRL_INTR_TEST_DEBUG_CABLE_RESVAL logic [0:0] undefined
ADC_CTRL_ALERT_TEST_RESVAL logic [0:0] undefined
ADC_CTRL_ALERT_TEST_FATAL_FAULT_RESVAL logic [0:0]
ADC_CTRL_PERMIT logic [3:0] undefined Register width information to check illegal writes

Types

Name Type Description
adc_ctrl_reg2hw_intr_state_reg_t struct packed {
logic q;
}		 ////////////////////////// Typedefs for registers // //////////////////////////
adc_ctrl_reg2hw_intr_enable_reg_t struct packed {
logic q;
}
adc_ctrl_reg2hw_intr_test_reg_t struct packed {
logic q;
logic qe;
}
adc_ctrl_reg2hw_alert_test_reg_t struct packed {
logic q;
logic qe;
}
adc_ctrl_reg2hw_adc_en_ctl_reg_t struct packed {
struct packed {
logic q;
} adc_enable;
struct packed {
logic q;
} oneshot_mode;
}
adc_ctrl_reg2hw_adc_pd_ctl_reg_t struct packed {
struct packed {
logic q;
} lp_mode;
struct packed {
logic [3:0] q;
} pwrup_time;
struct packed {
logic [23:0] q;
} wakeup_time;
}
adc_ctrl_reg2hw_adc_lp_sample_ctl_reg_t struct packed {
logic [7:0] q;
}
adc_ctrl_reg2hw_adc_sample_ctl_reg_t struct packed {
logic [15:0] q;
}
adc_ctrl_reg2hw_adc_fsm_rst_reg_t struct packed {
logic q;
}
adc_ctrl_reg2hw_adc_chn0_filter_ctl_mreg_t struct packed {
struct packed {
logic [9:0] q;
} min_v;
struct packed {
logic q;
} cond;
struct packed {
logic [9:0] q;
} max_v;
struct packed {
logic q;
} en;
}
adc_ctrl_reg2hw_adc_chn1_filter_ctl_mreg_t struct packed {
struct packed {
logic [9:0] q;
} min_v;
struct packed {
logic q;
} cond;
struct packed {
logic [9:0] q;
} max_v;
struct packed {
logic q;
} en;
}
adc_ctrl_reg2hw_adc_wakeup_ctl_reg_t struct packed {
logic [7:0] q;
}
adc_ctrl_reg2hw_filter_status_reg_t struct packed {
logic [7:0] q;
}
adc_ctrl_reg2hw_adc_intr_ctl_reg_t struct packed {
logic [8:0] q;
}
adc_ctrl_hw2reg_intr_state_reg_t struct packed {
logic d;
logic de;
}
adc_ctrl_hw2reg_adc_chn_val_mreg_t struct packed {
struct packed {
logic [1:0] d;
logic de;
} adc_chn_value_ext;
struct packed {
logic [9:0] d;
logic de;
} adc_chn_value;
struct packed {
logic [1:0] d;
logic de;
} adc_chn_value_intr_ext;
struct packed {
logic [9:0] d;
logic de;
} adc_chn_value_intr;
}
adc_ctrl_hw2reg_filter_status_reg_t struct packed {
logic [7:0] d;
logic de;
}
adc_ctrl_hw2reg_adc_intr_status_reg_t struct packed {
struct packed {
logic d;
logic de;
} cc_sink_det;
struct packed {
logic d;
logic de;
} cc_1a5_sink_det;
struct packed {
logic d;
logic de;
} cc_3a0_sink_det;
struct packed {
logic d;
logic de;
} cc_src_det;
struct packed {
logic d;
logic de;
} cc_1a5_src_det;
struct packed {
logic d;
logic de;
} cc_src_det_flip;
struct packed {
logic d;
logic de;
} cc_1a5_src_det_flip;
struct packed {
logic d;
logic de;
} cc_discon;
struct packed {
logic d;
logic de;
} oneshot;
}
adc_ctrl_reg2hw_adc_chn0_filter_ctl_mreg_t struct packed {
adc_ctrl_reg2hw_intr_state_reg_t intr_state;
adc_ctrl_reg2hw_intr_enable_reg_t intr_enable;
adc_ctrl_reg2hw_intr_test_reg_t intr_test;
adc_ctrl_reg2hw_alert_test_reg_t alert_test;
adc_ctrl_reg2hw_adc_en_ctl_reg_t adc_en_ctl;
adc_ctrl_reg2hw_adc_pd_ctl_reg_t adc_pd_ctl;
adc_ctrl_reg2hw_adc_lp_sample_ctl_reg_t adc_lp_sample_ctl;
adc_ctrl_reg2hw_adc_sample_ctl_reg_t adc_sample_ctl;
adc_ctrl_reg2hw_adc_fsm_rst_reg_t adc_fsm_rst;
adc_ctrl_reg2hw_adc_chn0_filter_ctl_mreg_t [7:0] adc_chn0_filter_ctl;
adc_ctrl_reg2hw_adc_chn1_filter_ctl_mreg_t [7:0] adc_chn1_filter_ctl;
adc_ctrl_reg2hw_adc_wakeup_ctl_reg_t adc_wakeup_ctl;
adc_ctrl_reg2hw_filter_status_reg_t filter_status;
adc_ctrl_reg2hw_adc_intr_ctl_reg_t adc_intr_ctl;
}		 Register -> HW type
adc_ctrl_hw2reg_adc_chn_val_mreg_t struct packed {
adc_ctrl_hw2reg_intr_state_reg_t intr_state;
adc_ctrl_hw2reg_adc_chn_val_mreg_t [1:0] adc_chn_val;
adc_ctrl_hw2reg_filter_status_reg_t filter_status;
adc_ctrl_hw2reg_adc_intr_status_reg_t adc_intr_status;
}		 HW -> register type