Entity: aes_ctr

Diagram

clk_i rst_ni sp2v_e incr_i [NumSlicesCtr-1:0] ctr_i sp2v_e ready_o alert_o [NumSlicesCtr-1:0] ctr_o [NumSlicesCtr-1:0] ctr_we_o

Description

Copyright lowRISC contributors. Licensed under the Apache License, Version 2.0, see LICENSE for details. SPDX-License-Identifier: Apache-2.0

AES counter for CTR mode

This module uses one counter with a width of SliceSizeCtr to iteratively increment the 128-bit counter value.

Ports

Port name Direction Type Description
clk_i input
rst_ni input
incr_i input sp2v_e
ready_o output sp2v_e
alert_o output
ctr_i input [NumSlicesCtr-1:0]
ctr_o output [NumSlicesCtr-1:0]
ctr_we_o output [NumSlicesCtr-1:0]

Signals

Name Type Description
aes_ctr_ns aes_ctr_e
aes_ctr_cs aes_ctr_e
ctr_slice_idx_d logic [SliceIdxWidth-1:0]
ctr_slice_idx_q logic [SliceIdxWidth-1:0]
ctr_carry_d logic
ctr_carry_q logic
ctr_i_rev logic [NumSlicesCtr-1:0][SliceSizeCtr-1:0] 8 times 2 bytes
ctr_o_rev logic [NumSlicesCtr-1:0][SliceSizeCtr-1:0] 8 times 2 bytes
ctr_we_o_rev sp2v_e [NumSlicesCtr-1:0]
ctr_we sp2v_e
ctr_i_slice logic [SliceSizeCtr-1:0]
ctr_o_slice logic [SliceSizeCtr-1:0]
ctr_value logic [SliceSizeCtr:0]
alert logic
incr sp2v_e
incr_err_d logic
incr_err_q logic
incr_raw logic [Sp2VWidth-1:0] Check sparsely encoded incr signal.
aes_ctr_cs_raw logic [StateWidth-1:0] This primitive is used to place a size-only constraint on the flops in order to prevent FSM state encoding optimizations.

Constants

Name Type Value Description
SliceIdxWidth int unsigned prim_util_pkg::vbits(NumSlicesCtr) Local parameters
StateWidth int 5 Types $ ./sparse-fsm-encode.py -d 3 -m 3 -n 5 \ -s 31468618 --language=sv
Hamming distance histogram:
0: -- 1: -- 2: -- 3:

Types

Name Type Description
aes_ctr_e enum logic [StateWidth-1:0] {
IDLE = 5'b01110,
INCR = 5'b11000,
ERROR = 5'b00001 }

Functions

Description
Reverse byte order - unrelated to NumSlicesCtr and SliceSizeCtr

Description
Reverse sp2v order

Processes

Type: always_ff

Description
Need to register errors in incr to avoid circular loops in the main controller related to start.

Type: always_comb

Description
/////////// Control // /////////// FSM

Type: always_ff

Description
Registers

Type: always_comb

Description
/////////// Outputs // /////////// Combine input and counter output.

Type: always_comb

Description
Generate the sliced write enable.

Instantiations