Package: aes_reg_pkg

Description

Copyright lowRISC contributors.
Licensed under the Apache License, Version 2.0, see LICENSE for details.
SPDX-License-Identifier: Apache-2.0

Register Package auto-generated by reggen containing data structure

Constants

Name Type Value Description
NumRegsKey int 8
NumRegsIv int 4
NumRegsData int 4
NumAlerts int 2
BlockAw int 7 Address widths within the block
BlockAw logic [BlockAw-1:0] undefined Register offsets
BlockAw logic [BlockAw-1:0] 4
BlockAw logic [BlockAw-1:0] 8
BlockAw logic [BlockAw-1:0] c
BlockAw logic [BlockAw-1:0] 10
BlockAw logic [BlockAw-1:0] 14
BlockAw logic [BlockAw-1:0] 18
BlockAw logic [BlockAw-1:0] c
BlockAw logic [BlockAw-1:0] 20
BlockAw logic [BlockAw-1:0] 24
BlockAw logic [BlockAw-1:0] 28
BlockAw logic [BlockAw-1:0] c
BlockAw logic [BlockAw-1:0] 30
BlockAw logic [BlockAw-1:0] 34
BlockAw logic [BlockAw-1:0] 38
BlockAw logic [BlockAw-1:0] c
BlockAw logic [BlockAw-1:0] 40
BlockAw logic [BlockAw-1:0] 44
BlockAw logic [BlockAw-1:0] 48
BlockAw logic [BlockAw-1:0] c
BlockAw logic [BlockAw-1:0] 50
BlockAw logic [BlockAw-1:0] 54
BlockAw logic [BlockAw-1:0] 58
BlockAw logic [BlockAw-1:0] c
BlockAw logic [BlockAw-1:0] 60
BlockAw logic [BlockAw-1:0] 64
BlockAw logic [BlockAw-1:0] 68
BlockAw logic [BlockAw-1:0] c
BlockAw logic [BlockAw-1:0] 70
BlockAw logic [BlockAw-1:0] 74
BlockAw logic [BlockAw-1:0] 78
BlockAw logic [BlockAw-1:0] c
AES_ALERT_TEST_RESVAL logic [1:0] undefined Reset values for hwext registers and their fields
AES_ALERT_TEST_RECOV_CTRL_UPDATE_ERR_RESVAL logic [0:0] undefined
AES_ALERT_TEST_FATAL_FAULT_RESVAL logic [0:0] undefined
AES_KEY_SHARE0_0_RESVAL logic [31:0] undefined
AES_KEY_SHARE0_0_KEY_SHARE0_0_RESVAL logic [31:0] undefined
AES_KEY_SHARE0_1_RESVAL logic [31:0] undefined
AES_KEY_SHARE0_1_KEY_SHARE0_1_RESVAL logic [31:0] undefined
AES_KEY_SHARE0_2_RESVAL logic [31:0] undefined
AES_KEY_SHARE0_2_KEY_SHARE0_2_RESVAL logic [31:0] undefined
AES_KEY_SHARE0_3_RESVAL logic [31:0] undefined
AES_KEY_SHARE0_3_KEY_SHARE0_3_RESVAL logic [31:0] undefined
AES_KEY_SHARE0_4_RESVAL logic [31:0] undefined
AES_KEY_SHARE0_4_KEY_SHARE0_4_RESVAL logic [31:0] undefined
AES_KEY_SHARE0_5_RESVAL logic [31:0] undefined
AES_KEY_SHARE0_5_KEY_SHARE0_5_RESVAL logic [31:0] undefined
AES_KEY_SHARE0_6_RESVAL logic [31:0] undefined
AES_KEY_SHARE0_6_KEY_SHARE0_6_RESVAL logic [31:0] undefined
AES_KEY_SHARE0_7_RESVAL logic [31:0] undefined
AES_KEY_SHARE0_7_KEY_SHARE0_7_RESVAL logic [31:0] undefined
AES_KEY_SHARE1_0_RESVAL logic [31:0] undefined
AES_KEY_SHARE1_0_KEY_SHARE1_0_RESVAL logic [31:0] undefined
AES_KEY_SHARE1_1_RESVAL logic [31:0] undefined
AES_KEY_SHARE1_1_KEY_SHARE1_1_RESVAL logic [31:0] undefined
AES_KEY_SHARE1_2_RESVAL logic [31:0] undefined
AES_KEY_SHARE1_2_KEY_SHARE1_2_RESVAL logic [31:0] undefined
AES_KEY_SHARE1_3_RESVAL logic [31:0] undefined
AES_KEY_SHARE1_3_KEY_SHARE1_3_RESVAL logic [31:0] undefined
AES_KEY_SHARE1_4_RESVAL logic [31:0] undefined
AES_KEY_SHARE1_4_KEY_SHARE1_4_RESVAL logic [31:0] undefined
AES_KEY_SHARE1_5_RESVAL logic [31:0] undefined
AES_KEY_SHARE1_5_KEY_SHARE1_5_RESVAL logic [31:0] undefined
AES_KEY_SHARE1_6_RESVAL logic [31:0] undefined
AES_KEY_SHARE1_6_KEY_SHARE1_6_RESVAL logic [31:0] undefined
AES_KEY_SHARE1_7_RESVAL logic [31:0] undefined
AES_KEY_SHARE1_7_KEY_SHARE1_7_RESVAL logic [31:0] undefined
AES_IV_0_RESVAL logic [31:0] undefined
AES_IV_0_IV_0_RESVAL logic [31:0] undefined
AES_IV_1_RESVAL logic [31:0] undefined
AES_IV_1_IV_1_RESVAL logic [31:0] undefined
AES_IV_2_RESVAL logic [31:0] undefined
AES_IV_2_IV_2_RESVAL logic [31:0] undefined
AES_IV_3_RESVAL logic [31:0] undefined
AES_IV_3_IV_3_RESVAL logic [31:0] undefined
AES_DATA_OUT_0_RESVAL logic [31:0] undefined
AES_DATA_OUT_0_DATA_OUT_0_RESVAL logic [31:0] undefined
AES_DATA_OUT_1_RESVAL logic [31:0] undefined
AES_DATA_OUT_1_DATA_OUT_1_RESVAL logic [31:0] undefined
AES_DATA_OUT_2_RESVAL logic [31:0] undefined
AES_DATA_OUT_2_DATA_OUT_2_RESVAL logic [31:0] undefined
AES_DATA_OUT_3_RESVAL logic [31:0] undefined
AES_DATA_OUT_3_DATA_OUT_3_RESVAL logic [31:0] undefined
AES_CTRL_SHADOWED_RESVAL logic [11:0] c0
AES_CTRL_SHADOWED_OPERATION_RESVAL logic [0:0] undefined
AES_CTRL_SHADOWED_MODE_RESVAL logic [5:0] 20
AES_CTRL_SHADOWED_KEY_LEN_RESVAL logic [2:0] undefined
AES_CTRL_SHADOWED_MANUAL_OPERATION_RESVAL logic [0:0] undefined
AES_CTRL_SHADOWED_FORCE_ZERO_MASKS_RESVAL logic [0:0]
AES_PERMIT logic [3:0] undefined Register width information to check illegal writes

Types

Name Type Description
aes_reg2hw_alert_test_reg_t struct packed {
struct packed {
logic q;
logic qe;
} recov_ctrl_update_err;
struct packed {
logic q;
logic qe;
} fatal_fault;
}		 ////////////////////////// Typedefs for registers // //////////////////////////
aes_reg2hw_key_share0_mreg_t struct packed {
logic [31:0] q;
logic qe;
}
aes_reg2hw_key_share1_mreg_t struct packed {
logic [31:0] q;
logic qe;
}
aes_reg2hw_iv_mreg_t struct packed {
logic [31:0] q;
logic qe;
}
aes_reg2hw_data_in_mreg_t struct packed {
logic [31:0] q;
logic qe;
}
aes_reg2hw_data_out_mreg_t struct packed {
logic [31:0] q;
logic re;
}
aes_reg2hw_ctrl_shadowed_reg_t struct packed {
struct packed {
logic q;
logic qe;
logic re;
} operation;
struct packed {
logic [5:0] q;
logic qe;
logic re;
} mode;
struct packed {
logic [2:0] q;
logic qe;
logic re;
} key_len;
struct packed {
logic q;
logic qe;
logic re;
} manual_operation;
struct packed {
logic q;
logic qe;
logic re;
} force_zero_masks;
}
aes_reg2hw_trigger_reg_t struct packed {
struct packed {
logic q;
} start;
struct packed {
logic q;
} key_iv_data_in_clear;
struct packed {
logic q;
} data_out_clear;
struct packed {
logic q;
} prng_reseed;
}
aes_reg2hw_status_reg_t struct packed {
struct packed {
logic q;
} output_lost;
}
aes_hw2reg_key_share0_mreg_t struct packed {
logic [31:0] d;
}
aes_hw2reg_key_share1_mreg_t struct packed {
logic [31:0] d;
}
aes_hw2reg_iv_mreg_t struct packed {
logic [31:0] d;
}
aes_hw2reg_data_in_mreg_t struct packed {
logic [31:0] d;
logic de;
}
aes_hw2reg_data_out_mreg_t struct packed {
logic [31:0] d;
}
aes_hw2reg_ctrl_shadowed_reg_t struct packed {
struct packed {
logic d;
} operation;
struct packed {
logic [5:0] d;
} mode;
struct packed {
logic [2:0] d;
} key_len;
struct packed {
logic d;
} manual_operation;
struct packed {
logic d;
} force_zero_masks;
}
aes_hw2reg_trigger_reg_t struct packed {
struct packed {
logic d;
logic de;
} start;
struct packed {
logic d;
logic de;
} key_iv_data_in_clear;
struct packed {
logic d;
logic de;
} data_out_clear;
struct packed {
logic d;
logic de;
} prng_reseed;
}
aes_hw2reg_status_reg_t struct packed {
struct packed {
logic d;
logic de;
} idle;
struct packed {
logic d;
logic de;
} stall;
struct packed {
logic d;
logic de;
} output_lost;
struct packed {
logic d;
logic de;
} output_valid;
struct packed {
logic d;
logic de;
} input_ready;
struct packed {
logic d;
logic de;
} alert_recov_ctrl_update_err;
struct packed {
logic d;
logic de;
} alert_fatal_fault;
}
aes_reg2hw_key_share0_mreg_t struct packed {
aes_reg2hw_alert_test_reg_t alert_test;
aes_reg2hw_key_share0_mreg_t [7:0] key_share0;
aes_reg2hw_key_share1_mreg_t [7:0] key_share1;
aes_reg2hw_iv_mreg_t [3:0] iv;
aes_reg2hw_data_in_mreg_t [3:0] data_in;
aes_reg2hw_data_out_mreg_t [3:0] data_out;
aes_reg2hw_ctrl_shadowed_reg_t ctrl_shadowed;
aes_reg2hw_trigger_reg_t trigger;
aes_reg2hw_status_reg_t status;
}		 Register -> HW type
aes_hw2reg_key_share0_mreg_t struct packed {
aes_hw2reg_key_share0_mreg_t [7:0] key_share0;
aes_hw2reg_key_share1_mreg_t [7:0] key_share1;
aes_hw2reg_iv_mreg_t [3:0] iv;
aes_hw2reg_data_in_mreg_t [3:0] data_in;
aes_hw2reg_data_out_mreg_t [3:0] data_out;
aes_hw2reg_ctrl_shadowed_reg_t ctrl_shadowed;
aes_hw2reg_trigger_reg_t trigger;
aes_hw2reg_status_reg_t status;
}		 HW -> register type