Entity: aes_reg_top

• File: aes_reg_top.sv

Diagram

Description

Ports

Port name	Direction	Type	Description
clk_i	input
rst_ni	input
tl_i	input
tl_o	output
reg2hw	output		Write
hw2reg	input		Read
intg_err_o	output		Integrity check errors
devmode_i	input		If 1, explicit error return for unmapped register access

Signals

Name	Type	Description
reg_we	logic	register signals
reg_re	logic
reg_addr	logic [AW-1:0]
reg_wdata	logic [DW-1:0]
reg_be	logic [DBW-1:0]
reg_rdata	logic [DW-1:0]
reg_error	logic
addrmiss	logic
wr_err	logic
reg_rdata_next	logic [DW-1:0]
reg_busy	logic
tl_reg_h2d	tlul_pkg::tl_h2d_t
tl_reg_d2h	tlul_pkg::tl_d2h_t
intg_err	logic	incoming payload check
intg_err_q	logic
tl_o_pre	tlul_pkg::tl_d2h_t	outgoing integrity generation
alert_test_we	logic	Define SW related signals Format: {wd
alert_test_recov_ctrl_update_err_wd	logic
alert_test_fatal_fault_wd	logic
key_share0_0_we	logic
key_share0_0_wd	logic [31:0]
key_share0_1_we	logic
key_share0_1_wd	logic [31:0]
key_share0_2_we	logic
key_share0_2_wd	logic [31:0]
key_share0_3_we	logic
key_share0_3_wd	logic [31:0]
key_share0_4_we	logic
key_share0_4_wd	logic [31:0]
key_share0_5_we	logic
key_share0_5_wd	logic [31:0]
key_share0_6_we	logic
key_share0_6_wd	logic [31:0]
key_share0_7_we	logic
key_share0_7_wd	logic [31:0]
key_share1_0_we	logic
key_share1_0_wd	logic [31:0]
key_share1_1_we	logic
key_share1_1_wd	logic [31:0]
key_share1_2_we	logic
key_share1_2_wd	logic [31:0]
key_share1_3_we	logic
key_share1_3_wd	logic [31:0]
key_share1_4_we	logic
key_share1_4_wd	logic [31:0]
key_share1_5_we	logic
key_share1_5_wd	logic [31:0]
key_share1_6_we	logic
key_share1_6_wd	logic [31:0]
key_share1_7_we	logic
key_share1_7_wd	logic [31:0]
iv_0_we	logic
iv_0_wd	logic [31:0]
iv_1_we	logic
iv_1_wd	logic [31:0]
iv_2_we	logic
iv_2_wd	logic [31:0]
iv_3_we	logic
iv_3_wd	logic [31:0]
data_in_0_we	logic
data_in_0_wd	logic [31:0]
data_in_1_we	logic
data_in_1_wd	logic [31:0]
data_in_2_we	logic
data_in_2_wd	logic [31:0]
data_in_3_we	logic
data_in_3_wd	logic [31:0]
data_out_0_re	logic
data_out_0_qs	logic [31:0]
data_out_1_re	logic
data_out_1_qs	logic [31:0]
data_out_2_re	logic
data_out_2_qs	logic [31:0]
data_out_3_re	logic
data_out_3_qs	logic [31:0]
ctrl_shadowed_re	logic
ctrl_shadowed_we	logic
ctrl_shadowed_operation_qs	logic
ctrl_shadowed_operation_wd	logic
ctrl_shadowed_mode_qs	logic [5:0]
ctrl_shadowed_mode_wd	logic [5:0]
ctrl_shadowed_key_len_qs	logic [2:0]
ctrl_shadowed_key_len_wd	logic [2:0]
ctrl_shadowed_manual_operation_qs	logic
ctrl_shadowed_manual_operation_wd	logic
ctrl_shadowed_force_zero_masks_qs	logic
ctrl_shadowed_force_zero_masks_wd	logic
trigger_we	logic
trigger_start_wd	logic
trigger_key_iv_data_in_clear_wd	logic
trigger_data_out_clear_wd	logic
trigger_prng_reseed_wd	logic
status_idle_qs	logic
status_stall_qs	logic
status_output_lost_qs	logic
status_output_valid_qs	logic
status_input_ready_qs	logic
status_alert_recov_ctrl_update_err_qs	logic
status_alert_fatal_fault_qs	logic
addr_hit	logic [31:0]
shadow_busy	logic	shadow busy
reg_busy_sel	logic	register busy
unused_wdata	logic	Unused signal tieoff wdata / byte enable are not always fully used add a blanket unused statement to handle lint waivers
unused_be	logic

Constants

Name	Type	Value	Description
AW	int	7
DW	int	32
DBW	int	DW/8	Byte Width

Processes

• unnamed: ( @(posedge clk_i or negedge rst_ni) )

• unnamed: ( )

• unnamed: ( )

• unnamed: ( )

• unnamed: ( )

Instantiations

• u_chk: tlul_cmd_intg_chk

• u_rsp_intg_gen: tlul_rsp_intg_gen

• u_reg_if: tlul_adapter_reg

• u_alert_test_recov_ctrl_update_err: prim_subreg_ext

• u_alert_test_fatal_fault: prim_subreg_ext

• u_ctrl_shadowed_operation: prim_subreg_ext

• u_ctrl_shadowed_mode: prim_subreg_ext

• u_ctrl_shadowed_key_len: prim_subreg_ext

• u_ctrl_shadowed_manual_operation: prim_subreg_ext

• u_ctrl_shadowed_force_zero_masks: prim_subreg_ext

• u_trigger_start: prim_subreg

• u_trigger_key_iv_data_in_clear: prim_subreg

• u_trigger_data_out_clear: prim_subreg

• u_trigger_prng_reseed: prim_subreg

• u_status_idle: prim_subreg

• u_status_stall: prim_subreg

• u_status_output_lost: prim_subreg

• u_status_output_valid: prim_subreg

• u_status_input_ready: prim_subreg

• u_status_alert_recov_ctrl_update_err: prim_subreg

• u_status_alert_fatal_fault: prim_subreg