Package: alert_handler_reg_pkg

Description

Copyright lowRISC contributors.
Licensed under the Apache License, Version 2.0, see LICENSE for details.
SPDX-License-Identifier: Apache-2.0

Register Package auto-generated by reggen containing data structure

Constants

Name Type Value Description
NAlerts int 4
EscCntDw int 32
AccuCntDw int 16
NAlerts logic [NAlerts-1:0] '0
N_CLASSES int 4
N_ESC_SEV int 4
N_PHASES int 4
N_LOC_ALERT int 7
PING_CNT_DW int 16
PHASE_DW int 2
CLASS_DW int 2
LOCAL_ALERT_ID_ALERT_PINGFAIL int 0
LOCAL_ALERT_ID_ESC_PINGFAIL int 1
LOCAL_ALERT_ID_ALERT_INTEGFAIL int 2
LOCAL_ALERT_ID_ESC_INTEGFAIL int 3
LOCAL_ALERT_ID_BUS_INTEGFAIL int 4
LOCAL_ALERT_ID_SHADOW_REG_UPDATE_ERROR int 5
LOCAL_ALERT_ID_SHADOW_REG_STORAGE_ERROR int 6
LOCAL_ALERT_ID_LAST int 6
BlockAw int 9 Address widths within the block
BlockAw logic [BlockAw-1:0] undefined Register offsets
BlockAw logic [BlockAw-1:0] 4
BlockAw logic [BlockAw-1:0] 8
BlockAw logic [BlockAw-1:0] c
BlockAw logic [BlockAw-1:0] 10
BlockAw logic [BlockAw-1:0] 14
BlockAw logic [BlockAw-1:0] 18
BlockAw logic [BlockAw-1:0] c
BlockAw logic [BlockAw-1:0] 20
BlockAw logic [BlockAw-1:0] 24
BlockAw logic [BlockAw-1:0] 28
BlockAw logic [BlockAw-1:0] c
BlockAw logic [BlockAw-1:0] 30
BlockAw logic [BlockAw-1:0] 34
BlockAw logic [BlockAw-1:0] 38
BlockAw logic [BlockAw-1:0] c
BlockAw logic [BlockAw-1:0] 40
BlockAw logic [BlockAw-1:0] 44
BlockAw logic [BlockAw-1:0] 48
BlockAw logic [BlockAw-1:0] c
BlockAw logic [BlockAw-1:0] 50
BlockAw logic [BlockAw-1:0] 54
BlockAw logic [BlockAw-1:0] 58
BlockAw logic [BlockAw-1:0] c
BlockAw logic [BlockAw-1:0] 60
BlockAw logic [BlockAw-1:0] 64
BlockAw logic [BlockAw-1:0] 68
BlockAw logic [BlockAw-1:0] c
BlockAw logic [BlockAw-1:0] 70
BlockAw logic [BlockAw-1:0] 74
BlockAw logic [BlockAw-1:0] 78
BlockAw logic [BlockAw-1:0] c
BlockAw logic [BlockAw-1:0] 80
BlockAw logic [BlockAw-1:0] 84
BlockAw logic [BlockAw-1:0] 88
BlockAw logic [BlockAw-1:0] c
BlockAw logic [BlockAw-1:0] 90
BlockAw logic [BlockAw-1:0] 94
BlockAw logic [BlockAw-1:0] 98
BlockAw logic [BlockAw-1:0] c
BlockAw logic [BlockAw-1:0] a0
BlockAw logic [BlockAw-1:0] a4
BlockAw logic [BlockAw-1:0] a8
BlockAw logic [BlockAw-1:0] ac
BlockAw logic [BlockAw-1:0] b0
BlockAw logic [BlockAw-1:0] b4
BlockAw logic [BlockAw-1:0] b8
BlockAw logic [BlockAw-1:0] bc
BlockAw logic [BlockAw-1:0] c0
BlockAw logic [BlockAw-1:0] c4
BlockAw logic [BlockAw-1:0] c8
BlockAw logic [BlockAw-1:0] cc
BlockAw logic [BlockAw-1:0] d0
BlockAw logic [BlockAw-1:0] d4
BlockAw logic [BlockAw-1:0] d8
BlockAw logic [BlockAw-1:0] dc
BlockAw logic [BlockAw-1:0] e0
BlockAw logic [BlockAw-1:0] e4
BlockAw logic [BlockAw-1:0] e8
BlockAw logic [BlockAw-1:0] ec
BlockAw logic [BlockAw-1:0] f0
BlockAw logic [BlockAw-1:0] f4
BlockAw logic [BlockAw-1:0] f8
BlockAw logic [BlockAw-1:0] fc
BlockAw logic [BlockAw-1:0] 100
BlockAw logic [BlockAw-1:0] 104
BlockAw logic [BlockAw-1:0] 108
BlockAw logic [BlockAw-1:0] c
BlockAw logic [BlockAw-1:0] 110
BlockAw logic [BlockAw-1:0] 114
BlockAw logic [BlockAw-1:0] 118
BlockAw logic [BlockAw-1:0] c
BlockAw logic [BlockAw-1:0] 120
BlockAw logic [BlockAw-1:0] 124
BlockAw logic [BlockAw-1:0] 128
BlockAw logic [BlockAw-1:0] c
BlockAw logic [BlockAw-1:0] 130
BlockAw logic [BlockAw-1:0] 134
BlockAw logic [BlockAw-1:0] 138
BlockAw logic [BlockAw-1:0] c
BlockAw logic [BlockAw-1:0] 140
BlockAw logic [BlockAw-1:0] 144
BlockAw logic [BlockAw-1:0] 148
BlockAw logic [BlockAw-1:0] c
BlockAw logic [BlockAw-1:0] 150
BlockAw logic [BlockAw-1:0] 154
BlockAw logic [BlockAw-1:0] 158
BlockAw logic [BlockAw-1:0] c
BlockAw logic [BlockAw-1:0] 160
BlockAw logic [BlockAw-1:0] 164
BlockAw logic [BlockAw-1:0] 168
BlockAw logic [BlockAw-1:0] c
BlockAw logic [BlockAw-1:0] 170
BlockAw logic [BlockAw-1:0] 174
BlockAw logic [BlockAw-1:0] 178
BlockAw logic [BlockAw-1:0] c
BlockAw logic [BlockAw-1:0] 180
BlockAw logic [BlockAw-1:0] 184
BlockAw logic [BlockAw-1:0] 188
BlockAw logic [BlockAw-1:0] c
BlockAw logic [BlockAw-1:0] 190
BlockAw logic [BlockAw-1:0] 194
BlockAw logic [BlockAw-1:0] 198
BlockAw logic [BlockAw-1:0] c
BlockAw logic [BlockAw-1:0] a0
BlockAw logic [BlockAw-1:0] a4
ALERT_HANDLER_INTR_TEST_RESVAL logic [3:0] undefined Reset values for hwext registers and their fields
ALERT_HANDLER_INTR_TEST_CLASSA_RESVAL logic [0:0] undefined
ALERT_HANDLER_INTR_TEST_CLASSB_RESVAL logic [0:0] undefined
ALERT_HANDLER_INTR_TEST_CLASSC_RESVAL logic [0:0] undefined
ALERT_HANDLER_INTR_TEST_CLASSD_RESVAL logic [0:0] undefined
ALERT_HANDLER_CLASSA_ACCUM_CNT_RESVAL logic [15:0] undefined
ALERT_HANDLER_CLASSA_ESC_CNT_RESVAL logic [31:0] undefined
ALERT_HANDLER_CLASSA_STATE_RESVAL logic [2:0] undefined
ALERT_HANDLER_CLASSB_ACCUM_CNT_RESVAL logic [15:0] undefined
ALERT_HANDLER_CLASSB_ESC_CNT_RESVAL logic [31:0] undefined
ALERT_HANDLER_CLASSB_STATE_RESVAL logic [2:0] undefined
ALERT_HANDLER_CLASSC_ACCUM_CNT_RESVAL logic [15:0] undefined
ALERT_HANDLER_CLASSC_ESC_CNT_RESVAL logic [31:0] undefined
ALERT_HANDLER_CLASSC_STATE_RESVAL logic [2:0] undefined
ALERT_HANDLER_CLASSD_ACCUM_CNT_RESVAL logic [15:0] undefined
ALERT_HANDLER_CLASSD_ESC_CNT_RESVAL logic [31:0] undefined
ALERT_HANDLER_CLASSD_STATE_RESVAL logic [2:0]
ALERT_HANDLER_PERMIT logic [3:0] undefined Register width information to check illegal writes

Types

Name Type Description
alert_handler_reg2hw_intr_state_reg_t struct packed {
struct packed {
logic q;
} classa;
struct packed {
logic q;
} classb;
struct packed {
logic q;
} classc;
struct packed {
logic q;
} classd;
}		 ////////////////////////// Typedefs for registers // //////////////////////////
alert_handler_reg2hw_intr_enable_reg_t struct packed {
struct packed {
logic q;
} classa;
struct packed {
logic q;
} classb;
struct packed {
logic q;
} classc;
struct packed {
logic q;
} classd;
}
alert_handler_reg2hw_intr_test_reg_t struct packed {
struct packed {
logic q;
logic qe;
} classa;
struct packed {
logic q;
logic qe;
} classb;
struct packed {
logic q;
logic qe;
} classc;
struct packed {
logic q;
logic qe;
} classd;
}
alert_handler_reg2hw_ping_timeout_cyc_shadowed_reg_t struct packed {
logic [15:0] q;
logic err_update;
logic err_storage;
}
alert_handler_reg2hw_ping_timer_en_shadowed_reg_t struct packed {
logic q;
logic err_update;
logic err_storage;
}
alert_handler_reg2hw_alert_regwen_mreg_t struct packed {
logic q;
}
alert_handler_reg2hw_alert_en_shadowed_mreg_t struct packed {
logic q;
logic err_update;
logic err_storage;
}
alert_handler_reg2hw_alert_class_shadowed_mreg_t struct packed {
logic [1:0] q;
logic err_update;
logic err_storage;
}
alert_handler_reg2hw_alert_cause_mreg_t struct packed {
logic q;
}
alert_handler_reg2hw_loc_alert_en_shadowed_mreg_t struct packed {
logic q;
logic err_update;
logic err_storage;
}
alert_handler_reg2hw_loc_alert_class_shadowed_mreg_t struct packed {
logic [1:0] q;
logic err_update;
logic err_storage;
}
alert_handler_reg2hw_loc_alert_cause_mreg_t struct packed {
logic q;
}
alert_handler_reg2hw_classa_ctrl_shadowed_reg_t struct packed {
struct packed {
logic q;
logic err_update;
logic err_storage;
} en;
struct packed {
logic q;
logic err_update;
logic err_storage;
} lock;
struct packed {
logic q;
logic err_update;
logic err_storage;
} en_e0;
struct packed {
logic q;
logic err_update;
logic err_storage;
} en_e1;
struct packed {
logic q;
logic err_update;
logic err_storage;
} en_e2;
struct packed {
logic q;
logic err_update;
logic err_storage;
} en_e3;
struct packed {
logic [1:0] q;
logic err_update;
logic err_storage;
} map_e0;
struct packed {
logic [1:0] q;
logic err_update;
logic err_storage;
} map_e1;
struct packed {
logic [1:0] q;
logic err_update;
logic err_storage;
} map_e2;
struct packed {
logic [1:0] q;
logic err_update;
logic err_storage;
} map_e3;
}
alert_handler_reg2hw_classa_clr_shadowed_reg_t struct packed {
logic q;
logic qe;
logic err_update;
logic err_storage;
}
alert_handler_reg2hw_classa_accum_thresh_shadowed_reg_t struct packed {
logic [15:0] q;
logic err_update;
logic err_storage;
}
alert_handler_reg2hw_classa_timeout_cyc_shadowed_reg_t struct packed {
logic [31:0] q;
logic err_update;
logic err_storage;
}
alert_handler_reg2hw_classa_crashdump_trigger_shadowed_reg_t struct packed {
logic [1:0] q;
logic err_update;
logic err_storage;
}
alert_handler_reg2hw_classa_phase0_cyc_shadowed_reg_t struct packed {
logic [31:0] q;
logic err_update;
logic err_storage;
}
alert_handler_reg2hw_classa_phase1_cyc_shadowed_reg_t struct packed {
logic [31:0] q;
logic err_update;
logic err_storage;
}
alert_handler_reg2hw_classa_phase2_cyc_shadowed_reg_t struct packed {
logic [31:0] q;
logic err_update;
logic err_storage;
}
alert_handler_reg2hw_classa_phase3_cyc_shadowed_reg_t struct packed {
logic [31:0] q;
logic err_update;
logic err_storage;
}
alert_handler_reg2hw_classb_ctrl_shadowed_reg_t struct packed {
struct packed {
logic q;
logic err_update;
logic err_storage;
} en;
struct packed {
logic q;
logic err_update;
logic err_storage;
} lock;
struct packed {
logic q;
logic err_update;
logic err_storage;
} en_e0;
struct packed {
logic q;
logic err_update;
logic err_storage;
} en_e1;
struct packed {
logic q;
logic err_update;
logic err_storage;
} en_e2;
struct packed {
logic q;
logic err_update;
logic err_storage;
} en_e3;
struct packed {
logic [1:0] q;
logic err_update;
logic err_storage;
} map_e0;
struct packed {
logic [1:0] q;
logic err_update;
logic err_storage;
} map_e1;
struct packed {
logic [1:0] q;
logic err_update;
logic err_storage;
} map_e2;
struct packed {
logic [1:0] q;
logic err_update;
logic err_storage;
} map_e3;
}
alert_handler_reg2hw_classb_clr_shadowed_reg_t struct packed {
logic q;
logic qe;
logic err_update;
logic err_storage;
}
alert_handler_reg2hw_classb_accum_thresh_shadowed_reg_t struct packed {
logic [15:0] q;
logic err_update;
logic err_storage;
}
alert_handler_reg2hw_classb_timeout_cyc_shadowed_reg_t struct packed {
logic [31:0] q;
logic err_update;
logic err_storage;
}
alert_handler_reg2hw_classb_crashdump_trigger_shadowed_reg_t struct packed {
logic [1:0] q;
logic err_update;
logic err_storage;
}
alert_handler_reg2hw_classb_phase0_cyc_shadowed_reg_t struct packed {
logic [31:0] q;
logic err_update;
logic err_storage;
}
alert_handler_reg2hw_classb_phase1_cyc_shadowed_reg_t struct packed {
logic [31:0] q;
logic err_update;
logic err_storage;
}
alert_handler_reg2hw_classb_phase2_cyc_shadowed_reg_t struct packed {
logic [31:0] q;
logic err_update;
logic err_storage;
}
alert_handler_reg2hw_classb_phase3_cyc_shadowed_reg_t struct packed {
logic [31:0] q;
logic err_update;
logic err_storage;
}
alert_handler_reg2hw_classc_ctrl_shadowed_reg_t struct packed {
struct packed {
logic q;
logic err_update;
logic err_storage;
} en;
struct packed {
logic q;
logic err_update;
logic err_storage;
} lock;
struct packed {
logic q;
logic err_update;
logic err_storage;
} en_e0;
struct packed {
logic q;
logic err_update;
logic err_storage;
} en_e1;
struct packed {
logic q;
logic err_update;
logic err_storage;
} en_e2;
struct packed {
logic q;
logic err_update;
logic err_storage;
} en_e3;
struct packed {
logic [1:0] q;
logic err_update;
logic err_storage;
} map_e0;
struct packed {
logic [1:0] q;
logic err_update;
logic err_storage;
} map_e1;
struct packed {
logic [1:0] q;
logic err_update;
logic err_storage;
} map_e2;
struct packed {
logic [1:0] q;
logic err_update;
logic err_storage;
} map_e3;
}
alert_handler_reg2hw_classc_clr_shadowed_reg_t struct packed {
logic q;
logic qe;
logic err_update;
logic err_storage;
}
alert_handler_reg2hw_classc_accum_thresh_shadowed_reg_t struct packed {
logic [15:0] q;
logic err_update;
logic err_storage;
}
alert_handler_reg2hw_classc_timeout_cyc_shadowed_reg_t struct packed {
logic [31:0] q;
logic err_update;
logic err_storage;
}
alert_handler_reg2hw_classc_crashdump_trigger_shadowed_reg_t struct packed {
logic [1:0] q;
logic err_update;
logic err_storage;
}
alert_handler_reg2hw_classc_phase0_cyc_shadowed_reg_t struct packed {
logic [31:0] q;
logic err_update;
logic err_storage;
}
alert_handler_reg2hw_classc_phase1_cyc_shadowed_reg_t struct packed {
logic [31:0] q;
logic err_update;
logic err_storage;
}
alert_handler_reg2hw_classc_phase2_cyc_shadowed_reg_t struct packed {
logic [31:0] q;
logic err_update;
logic err_storage;
}
alert_handler_reg2hw_classc_phase3_cyc_shadowed_reg_t struct packed {
logic [31:0] q;
logic err_update;
logic err_storage;
}
alert_handler_reg2hw_classd_ctrl_shadowed_reg_t struct packed {
struct packed {
logic q;
logic err_update;
logic err_storage;
} en;
struct packed {
logic q;
logic err_update;
logic err_storage;
} lock;
struct packed {
logic q;
logic err_update;
logic err_storage;
} en_e0;
struct packed {
logic q;
logic err_update;
logic err_storage;
} en_e1;
struct packed {
logic q;
logic err_update;
logic err_storage;
} en_e2;
struct packed {
logic q;
logic err_update;
logic err_storage;
} en_e3;
struct packed {
logic [1:0] q;
logic err_update;
logic err_storage;
} map_e0;
struct packed {
logic [1:0] q;
logic err_update;
logic err_storage;
} map_e1;
struct packed {
logic [1:0] q;
logic err_update;
logic err_storage;
} map_e2;
struct packed {
logic [1:0] q;
logic err_update;
logic err_storage;
} map_e3;
}
alert_handler_reg2hw_classd_clr_shadowed_reg_t struct packed {
logic q;
logic qe;
logic err_update;
logic err_storage;
}
alert_handler_reg2hw_classd_accum_thresh_shadowed_reg_t struct packed {
logic [15:0] q;
logic err_update;
logic err_storage;
}
alert_handler_reg2hw_classd_timeout_cyc_shadowed_reg_t struct packed {
logic [31:0] q;
logic err_update;
logic err_storage;
}
alert_handler_reg2hw_classd_crashdump_trigger_shadowed_reg_t struct packed {
logic [1:0] q;
logic err_update;
logic err_storage;
}
alert_handler_reg2hw_classd_phase0_cyc_shadowed_reg_t struct packed {
logic [31:0] q;
logic err_update;
logic err_storage;
}
alert_handler_reg2hw_classd_phase1_cyc_shadowed_reg_t struct packed {
logic [31:0] q;
logic err_update;
logic err_storage;
}
alert_handler_reg2hw_classd_phase2_cyc_shadowed_reg_t struct packed {
logic [31:0] q;
logic err_update;
logic err_storage;
}
alert_handler_reg2hw_classd_phase3_cyc_shadowed_reg_t struct packed {
logic [31:0] q;
logic err_update;
logic err_storage;
}
alert_handler_hw2reg_intr_state_reg_t struct packed {
struct packed {
logic d;
logic de;
} classa;
struct packed {
logic d;
logic de;
} classb;
struct packed {
logic d;
logic de;
} classc;
struct packed {
logic d;
logic de;
} classd;
}
alert_handler_hw2reg_alert_cause_mreg_t struct packed {
logic d;
logic de;
}
alert_handler_hw2reg_loc_alert_cause_mreg_t struct packed {
logic d;
logic de;
}
alert_handler_hw2reg_classa_clr_regwen_reg_t struct packed {
logic d;
logic de;
}
alert_handler_hw2reg_classa_accum_cnt_reg_t struct packed {
logic [15:0] d;
}
alert_handler_hw2reg_classa_esc_cnt_reg_t struct packed {
logic [31:0] d;
}
alert_handler_hw2reg_classa_state_reg_t struct packed {
logic [2:0] d;
}
alert_handler_hw2reg_classb_clr_regwen_reg_t struct packed {
logic d;
logic de;
}
alert_handler_hw2reg_classb_accum_cnt_reg_t struct packed {
logic [15:0] d;
}
alert_handler_hw2reg_classb_esc_cnt_reg_t struct packed {
logic [31:0] d;
}
alert_handler_hw2reg_classb_state_reg_t struct packed {
logic [2:0] d;
}
alert_handler_hw2reg_classc_clr_regwen_reg_t struct packed {
logic d;
logic de;
}
alert_handler_hw2reg_classc_accum_cnt_reg_t struct packed {
logic [15:0] d;
}
alert_handler_hw2reg_classc_esc_cnt_reg_t struct packed {
logic [31:0] d;
}
alert_handler_hw2reg_classc_state_reg_t struct packed {
logic [2:0] d;
}
alert_handler_hw2reg_classd_clr_regwen_reg_t struct packed {
logic d;
logic de;
}
alert_handler_hw2reg_classd_accum_cnt_reg_t struct packed {
logic [15:0] d;
}
alert_handler_hw2reg_classd_esc_cnt_reg_t struct packed {
logic [31:0] d;
}
alert_handler_hw2reg_classd_state_reg_t struct packed {
logic [2:0] d;
}
alert_handler_reg2hw_alert_regwen_mreg_t struct packed {
alert_handler_reg2hw_intr_state_reg_t intr_state;
alert_handler_reg2hw_intr_enable_reg_t intr_enable;
alert_handler_reg2hw_intr_test_reg_t intr_test;
alert_handler_reg2hw_ping_timeout_cyc_shadowed_reg_t ping_timeout_cyc_shadowed;
alert_handler_reg2hw_ping_timer_en_shadowed_reg_t ping_timer_en_shadowed;
alert_handler_reg2hw_alert_regwen_mreg_t [3:0] alert_regwen;
alert_handler_reg2hw_alert_en_shadowed_mreg_t [3:0] alert_en_shadowed;
alert_handler_reg2hw_alert_class_shadowed_mreg_t [3:0] alert_class_shadowed;
alert_handler_reg2hw_alert_cause_mreg_t [3:0] alert_cause;
alert_handler_reg2hw_loc_alert_en_shadowed_mreg_t [6:0] loc_alert_en_shadowed;
alert_handler_reg2hw_loc_alert_class_shadowed_mreg_t [6:0] loc_alert_class_shadowed;
alert_handler_reg2hw_loc_alert_cause_mreg_t [6:0] loc_alert_cause;
alert_handler_reg2hw_classa_ctrl_shadowed_reg_t classa_ctrl_shadowed;
alert_handler_reg2hw_classa_clr_shadowed_reg_t classa_clr_shadowed;
alert_handler_reg2hw_classa_accum_thresh_shadowed_reg_t classa_accum_thresh_shadowed;
alert_handler_reg2hw_classa_timeout_cyc_shadowed_reg_t classa_timeout_cyc_shadowed;
alert_handler_reg2hw_classa_crashdump_trigger_shadowed_reg_t classa_crashdump_trigger_shadowed;
alert_handler_reg2hw_classa_phase0_cyc_shadowed_reg_t classa_phase0_cyc_shadowed;
alert_handler_reg2hw_classa_phase1_cyc_shadowed_reg_t classa_phase1_cyc_shadowed;
alert_handler_reg2hw_classa_phase2_cyc_shadowed_reg_t classa_phase2_cyc_shadowed;
alert_handler_reg2hw_classa_phase3_cyc_shadowed_reg_t classa_phase3_cyc_shadowed;
alert_handler_reg2hw_classb_ctrl_shadowed_reg_t classb_ctrl_shadowed;
alert_handler_reg2hw_classb_clr_shadowed_reg_t classb_clr_shadowed;
alert_handler_reg2hw_classb_accum_thresh_shadowed_reg_t classb_accum_thresh_shadowed;
alert_handler_reg2hw_classb_timeout_cyc_shadowed_reg_t classb_timeout_cyc_shadowed;
alert_handler_reg2hw_classb_crashdump_trigger_shadowed_reg_t classb_crashdump_trigger_shadowed;
alert_handler_reg2hw_classb_phase0_cyc_shadowed_reg_t classb_phase0_cyc_shadowed;
alert_handler_reg2hw_classb_phase1_cyc_shadowed_reg_t classb_phase1_cyc_shadowed;
alert_handler_reg2hw_classb_phase2_cyc_shadowed_reg_t classb_phase2_cyc_shadowed;
alert_handler_reg2hw_classb_phase3_cyc_shadowed_reg_t classb_phase3_cyc_shadowed;
alert_handler_reg2hw_classc_ctrl_shadowed_reg_t classc_ctrl_shadowed;
alert_handler_reg2hw_classc_clr_shadowed_reg_t classc_clr_shadowed;
alert_handler_reg2hw_classc_accum_thresh_shadowed_reg_t classc_accum_thresh_shadowed;
alert_handler_reg2hw_classc_timeout_cyc_shadowed_reg_t classc_timeout_cyc_shadowed;
alert_handler_reg2hw_classc_crashdump_trigger_shadowed_reg_t classc_crashdump_trigger_shadowed;
alert_handler_reg2hw_classc_phase0_cyc_shadowed_reg_t classc_phase0_cyc_shadowed;
alert_handler_reg2hw_classc_phase1_cyc_shadowed_reg_t classc_phase1_cyc_shadowed;
alert_handler_reg2hw_classc_phase2_cyc_shadowed_reg_t classc_phase2_cyc_shadowed;
alert_handler_reg2hw_classc_phase3_cyc_shadowed_reg_t classc_phase3_cyc_shadowed;
alert_handler_reg2hw_classd_ctrl_shadowed_reg_t classd_ctrl_shadowed;
alert_handler_reg2hw_classd_clr_shadowed_reg_t classd_clr_shadowed;
alert_handler_reg2hw_classd_accum_thresh_shadowed_reg_t classd_accum_thresh_shadowed;
alert_handler_reg2hw_classd_timeout_cyc_shadowed_reg_t classd_timeout_cyc_shadowed;
alert_handler_reg2hw_classd_crashdump_trigger_shadowed_reg_t classd_crashdump_trigger_shadowed;
alert_handler_reg2hw_classd_phase0_cyc_shadowed_reg_t classd_phase0_cyc_shadowed;
alert_handler_reg2hw_classd_phase1_cyc_shadowed_reg_t classd_phase1_cyc_shadowed;
alert_handler_reg2hw_classd_phase2_cyc_shadowed_reg_t classd_phase2_cyc_shadowed;
alert_handler_reg2hw_classd_phase3_cyc_shadowed_reg_t classd_phase3_cyc_shadowed;
}		 Register -> HW type
alert_handler_hw2reg_alert_cause_mreg_t struct packed {
alert_handler_hw2reg_intr_state_reg_t intr_state;
alert_handler_hw2reg_alert_cause_mreg_t [3:0] alert_cause;
alert_handler_hw2reg_loc_alert_cause_mreg_t [6:0] loc_alert_cause;
alert_handler_hw2reg_classa_clr_regwen_reg_t classa_clr_regwen;
alert_handler_hw2reg_classa_accum_cnt_reg_t classa_accum_cnt;
alert_handler_hw2reg_classa_esc_cnt_reg_t classa_esc_cnt;
alert_handler_hw2reg_classa_state_reg_t classa_state;
alert_handler_hw2reg_classb_clr_regwen_reg_t classb_clr_regwen;
alert_handler_hw2reg_classb_accum_cnt_reg_t classb_accum_cnt;
alert_handler_hw2reg_classb_esc_cnt_reg_t classb_esc_cnt;
alert_handler_hw2reg_classb_state_reg_t classb_state;
alert_handler_hw2reg_classc_clr_regwen_reg_t classc_clr_regwen;
alert_handler_hw2reg_classc_accum_cnt_reg_t classc_accum_cnt;
alert_handler_hw2reg_classc_esc_cnt_reg_t classc_esc_cnt;
alert_handler_hw2reg_classc_state_reg_t classc_state;
alert_handler_hw2reg_classd_clr_regwen_reg_t classd_clr_regwen;
alert_handler_hw2reg_classd_accum_cnt_reg_t classd_accum_cnt;
alert_handler_hw2reg_classd_esc_cnt_reg_t classd_esc_cnt;
alert_handler_hw2reg_classd_state_reg_t classd_state;
}		 HW -> register type