Entity: aon_timer_reg_top

• File: aon_timer_reg_top.sv

Diagram

Description

Ports

Port name	Direction	Type	Description
clk_i	input
rst_ni	input
clk_aon_i	input
rst_aon_ni	input
tl_i	input
tl_o	output
reg2hw	output		Write
hw2reg	input		Read
intg_err_o	output		Integrity check errors
devmode_i	input		If 1, explicit error return for unmapped register access

Signals

Name	Type	Description
reg_we	logic	register signals
reg_re	logic
reg_addr	logic [AW-1:0]
reg_wdata	logic [DW-1:0]
reg_be	logic [DBW-1:0]
reg_rdata	logic [DW-1:0]
reg_error	logic
addrmiss	logic
wr_err	logic
reg_rdata_next	logic [DW-1:0]
reg_busy	logic
tl_reg_h2d	tlul_pkg::tl_h2d_t
tl_reg_d2h	tlul_pkg::tl_d2h_t
intg_err	logic	incoming payload check
intg_err_q	logic
tl_o_pre	tlul_pkg::tl_d2h_t	outgoing integrity generation
sync_aon_update	logic	cdc oversampling signals
alert_test_we	logic	Define SW related signals Format: {wd
alert_test_wd	logic
wkup_ctrl_we	logic
wkup_ctrl_qs	logic [12:0]
wkup_ctrl_busy	logic
wkup_thold_we	logic
wkup_thold_qs	logic [31:0]
wkup_thold_busy	logic
wkup_count_we	logic
wkup_count_qs	logic [31:0]
wkup_count_busy	logic
wdog_regwen_we	logic
wdog_regwen_qs	logic
wdog_regwen_wd	logic
wdog_ctrl_we	logic
wdog_ctrl_qs	logic [1:0]
wdog_ctrl_busy	logic
wdog_bark_thold_we	logic
wdog_bark_thold_qs	logic [31:0]
wdog_bark_thold_busy	logic
wdog_bite_thold_we	logic
wdog_bite_thold_qs	logic [31:0]
wdog_bite_thold_busy	logic
wdog_count_we	logic
wdog_count_qs	logic [31:0]
wdog_count_busy	logic
intr_state_we	logic
intr_state_wkup_timer_expired_qs	logic
intr_state_wkup_timer_expired_wd	logic
intr_state_wdog_timer_expired_qs	logic
intr_state_wdog_timer_expired_wd	logic
intr_test_we	logic
intr_test_wkup_timer_expired_wd	logic
intr_test_wdog_timer_expired_wd	logic
wkup_cause_we	logic
wkup_cause_qs	logic [0:0]
wkup_cause_busy	logic
aon_wkup_ctrl_enable_qs_int	logic	Define register CDC handling. CDC handling is done on a per-reg instead of per-field boundary.
aon_wkup_ctrl_prescaler_qs_int	logic [11:0]
aon_wkup_ctrl_d	logic [12:0]
aon_wkup_ctrl_wdata	logic [12:0]
aon_wkup_ctrl_we	logic
unused_aon_wkup_ctrl_wdata	logic
aon_wkup_thold_qs_int	logic [31:0]
aon_wkup_thold_d	logic [31:0]
aon_wkup_thold_wdata	logic [31:0]
aon_wkup_thold_we	logic
unused_aon_wkup_thold_wdata	logic
aon_wkup_count_qs_int	logic [31:0]
aon_wkup_count_d	logic [31:0]
aon_wkup_count_wdata	logic [31:0]
aon_wkup_count_we	logic
unused_aon_wkup_count_wdata	logic
aon_wdog_ctrl_enable_qs_int	logic
aon_wdog_ctrl_pause_in_sleep_qs_int	logic
aon_wdog_ctrl_d	logic [1:0]
aon_wdog_ctrl_wdata	logic [1:0]
aon_wdog_ctrl_we	logic
unused_aon_wdog_ctrl_wdata	logic
aon_wdog_ctrl_regwen	logic
aon_wdog_bark_thold_qs_int	logic [31:0]
aon_wdog_bark_thold_d	logic [31:0]
aon_wdog_bark_thold_wdata	logic [31:0]
aon_wdog_bark_thold_we	logic
unused_aon_wdog_bark_thold_wdata	logic
aon_wdog_bark_thold_regwen	logic
aon_wdog_bite_thold_qs_int	logic [31:0]
aon_wdog_bite_thold_d	logic [31:0]
aon_wdog_bite_thold_wdata	logic [31:0]
aon_wdog_bite_thold_we	logic
unused_aon_wdog_bite_thold_wdata	logic
aon_wdog_bite_thold_regwen	logic
aon_wdog_count_qs_int	logic [31:0]
aon_wdog_count_d	logic [31:0]
aon_wdog_count_wdata	logic [31:0]
aon_wdog_count_we	logic
unused_aon_wdog_count_wdata	logic
aon_wkup_cause_qs_int	logic
aon_wkup_cause_d	logic [0:0]
aon_wkup_cause_wdata	logic [0:0]
aon_wkup_cause_we	logic
unused_aon_wkup_cause_wdata	logic
addr_hit	logic [11:0]
shadow_busy	logic	shadow busy
reg_busy_sel	logic	register busy
unused_wdata	logic	Unused signal tieoff wdata / byte enable are not always fully used add a blanket unused statement to handle lint waivers
unused_be	logic

Constants

Name	Type	Value	Description
AW	int	6
DW	int	32
DBW	int	DW/8	Byte Width

Processes

• unnamed: ( @(posedge clk_i or negedge rst_ni) )

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Instantiations

• u_chk: tlul_cmd_intg_chk

• u_rsp_intg_gen: tlul_rsp_intg_gen

• u_reg_if: tlul_adapter_reg

• u_aon_tgl: prim_pulse_sync

• u_wkup_ctrl_cdc: prim_reg_cdc

• u_wkup_thold_cdc: prim_reg_cdc

• u_wkup_count_cdc: prim_reg_cdc

• u_wdog_ctrl_cdc: prim_reg_cdc

• u_wdog_bark_thold_cdc: prim_reg_cdc

• u_wdog_bite_thold_cdc: prim_reg_cdc

• u_wdog_count_cdc: prim_reg_cdc

• u_wkup_cause_cdc: prim_reg_cdc

• u_alert_test: prim_subreg_ext

• u_wkup_ctrl_enable: prim_subreg

• u_wkup_ctrl_prescaler: prim_subreg

• u_wkup_thold: prim_subreg

• u_wkup_count: prim_subreg

• u_wdog_regwen: prim_subreg

• u_wdog_ctrl_enable: prim_subreg

• u_wdog_ctrl_pause_in_sleep: prim_subreg

• u_wdog_bark_thold: prim_subreg

• u_wdog_bite_thold: prim_subreg

• u_wdog_count: prim_subreg

• u_intr_state_wkup_timer_expired: prim_subreg

• u_intr_state_wdog_timer_expired: prim_subreg

• u_intr_test_wkup_timer_expired: prim_subreg_ext

• u_intr_test_wdog_timer_expired: prim_subreg_ext

• u_wkup_cause: prim_subreg