Entity: csrng_reg_top
- File: csrng_reg_top.sv
Diagram
Description
Copyright lowRISC contributors. Licensed under the Apache License, Version 2.0, see LICENSE for details. SPDX-License-Identifier: Apache-2.0
Register Top module auto-generated by reggen
Ports
| Port name | Direction | Type | Description |
|---|---|---|---|
| clk_i | input | ||
| rst_ni | input | ||
| tl_i | input | ||
| tl_o | output | ||
| reg2hw | output | Write | |
| hw2reg | input | Read | |
| intg_err_o | output | Integrity check errors | |
| devmode_i | input | If 1, explicit error return for unmapped register access |
Signals
| Name | Type | Description |
|---|---|---|
| reg_we | logic | register signals |
| reg_re | logic | |
| reg_addr | logic [AW-1:0] | |
| reg_wdata | logic [DW-1:0] | |
| reg_be | logic [DBW-1:0] | |
| reg_rdata | logic [DW-1:0] | |
| reg_error | logic | |
| addrmiss | logic | |
| wr_err | logic | |
| reg_rdata_next | logic [DW-1:0] | |
| reg_busy | logic | |
| tl_reg_h2d | tlul_pkg::tl_h2d_t | |
| tl_reg_d2h | tlul_pkg::tl_d2h_t | |
| intg_err | logic | incoming payload check |
| intg_err_q | logic | |
| tl_o_pre | tlul_pkg::tl_d2h_t | outgoing integrity generation |
| intr_state_we | logic | Define SW related signals Format: |
| intr_state_cs_cmd_req_done_qs | logic | |
| intr_state_cs_cmd_req_done_wd | logic | |
| intr_state_cs_entropy_req_qs | logic | |
| intr_state_cs_entropy_req_wd | logic | |
| intr_state_cs_hw_inst_exc_qs | logic | |
| intr_state_cs_hw_inst_exc_wd | logic | |
| intr_state_cs_fatal_err_qs | logic | |
| intr_state_cs_fatal_err_wd | logic | |
| intr_enable_we | logic | |
| intr_enable_cs_cmd_req_done_qs | logic | |
| intr_enable_cs_cmd_req_done_wd | logic | |
| intr_enable_cs_entropy_req_qs | logic | |
| intr_enable_cs_entropy_req_wd | logic | |
| intr_enable_cs_hw_inst_exc_qs | logic | |
| intr_enable_cs_hw_inst_exc_wd | logic | |
| intr_enable_cs_fatal_err_qs | logic | |
| intr_enable_cs_fatal_err_wd | logic | |
| intr_test_we | logic | |
| intr_test_cs_cmd_req_done_wd | logic | |
| intr_test_cs_entropy_req_wd | logic | |
| intr_test_cs_hw_inst_exc_wd | logic | |
| intr_test_cs_fatal_err_wd | logic | |
| alert_test_we | logic | |
| alert_test_recov_alert_wd | logic | |
| alert_test_fatal_alert_wd | logic | |
| regwen_we | logic | |
| regwen_qs | logic | |
| regwen_wd | logic | |
| ctrl_we | logic | |
| ctrl_enable_qs | logic [3:0] | |
| ctrl_enable_wd | logic [3:0] | |
| ctrl_sw_app_enable_qs | logic [3:0] | |
| ctrl_sw_app_enable_wd | logic [3:0] | |
| ctrl_read_int_state_qs | logic [3:0] | |
| ctrl_read_int_state_wd | logic [3:0] | |
| cmd_req_we | logic | |
| cmd_req_wd | logic [31:0] | |
| sw_cmd_sts_cmd_rdy_qs | logic | |
| sw_cmd_sts_cmd_sts_qs | logic | |
| genbits_vld_re | logic | |
| genbits_vld_genbits_vld_qs | logic | |
| genbits_vld_genbits_fips_qs | logic | |
| genbits_re | logic | |
| genbits_qs | logic [31:0] | |
| int_state_num_we | logic | |
| int_state_num_qs | logic [3:0] | |
| int_state_num_wd | logic [3:0] | |
| int_state_val_re | logic | |
| int_state_val_qs | logic [31:0] | |
| hw_exc_sts_we | logic | |
| hw_exc_sts_qs | logic [14:0] | |
| hw_exc_sts_wd | logic [14:0] | |
| recov_alert_sts_we | logic | |
| recov_alert_sts_enable_field_alert_qs | logic | |
| recov_alert_sts_enable_field_alert_wd | logic | |
| recov_alert_sts_sw_app_enable_field_alert_qs | logic | |
| recov_alert_sts_sw_app_enable_field_alert_wd | logic | |
| recov_alert_sts_read_int_state_field_alert_qs | logic | |
| recov_alert_sts_read_int_state_field_alert_wd | logic | |
| err_code_sfifo_cmd_err_qs | logic | |
| err_code_sfifo_genbits_err_qs | logic | |
| err_code_sfifo_cmdreq_err_qs | logic | |
| err_code_sfifo_rcstage_err_qs | logic | |
| err_code_sfifo_keyvrc_err_qs | logic | |
| err_code_sfifo_updreq_err_qs | logic | |
| err_code_sfifo_bencreq_err_qs | logic | |
| err_code_sfifo_bencack_err_qs | logic | |
| err_code_sfifo_pdata_err_qs | logic | |
| err_code_sfifo_final_err_qs | logic | |
| err_code_sfifo_gbencack_err_qs | logic | |
| err_code_sfifo_grcstage_err_qs | logic | |
| err_code_sfifo_ggenreq_err_qs | logic | |
| err_code_sfifo_gadstage_err_qs | logic | |
| err_code_sfifo_ggenbits_err_qs | logic | |
| err_code_sfifo_blkenc_err_qs | logic | |
| err_code_cmd_stage_sm_err_qs | logic | |
| err_code_main_sm_err_qs | logic | |
| err_code_drbg_gen_sm_err_qs | logic | |
| err_code_drbg_updbe_sm_err_qs | logic | |
| err_code_drbg_updob_sm_err_qs | logic | |
| err_code_aes_cipher_sm_err_qs | logic | |
| err_code_fifo_write_err_qs | logic | |
| err_code_fifo_read_err_qs | logic | |
| err_code_fifo_state_err_qs | logic | |
| err_code_test_we | logic | |
| err_code_test_qs | logic [4:0] | |
| err_code_test_wd | logic [4:0] | |
| sel_tracking_sm_we | logic | |
| sel_tracking_sm_wd | logic [1:0] | |
| tracking_sm_obs_tracking_sm_obs0_qs | logic [7:0] | |
| tracking_sm_obs_tracking_sm_obs1_qs | logic [7:0] | |
| tracking_sm_obs_tracking_sm_obs2_qs | logic [7:0] | |
| tracking_sm_obs_tracking_sm_obs3_qs | logic [7:0] | |
| addr_hit | logic [17:0] | |
| shadow_busy | logic | shadow busy |
| reg_busy_sel | logic | register busy |
| unused_wdata | logic | Unused signal tieoff wdata / byte enable are not always fully used add a blanket unused statement to handle lint waivers |
| unused_be | logic |
Constants
| Name | Type | Value | Description |
|---|---|---|---|
| AW | int | 7 | |
| DW | int | 32 | |
| DBW | int | DW/8 | Byte Width |
Processes
- unnamed: ( @(posedge clk_i or negedge rst_ni) )
Type: always_ff
- unnamed: ( )
Type: always_comb
- unnamed: ( )
Type: always_comb
Description
Check sub-word write is permitted
- unnamed: ( )
Type: always_comb
Description
Read data return
- unnamed: ( )
Type: always_comb
Instantiations
- u_chk: tlul_cmd_intg_chk
- u_rsp_intg_gen: tlul_rsp_intg_gen
- u_reg_if: tlul_adapter_reg
- u_intr_state_cs_cmd_req_done: prim_subreg
Description
Register instances
R[intr_state]: V(False)
F[cs_cmd_req_done]: 0:0
- u_intr_state_cs_entropy_req: prim_subreg
Description
F[cs_entropy_req]: 1:1
- u_intr_state_cs_hw_inst_exc: prim_subreg
Description
F[cs_hw_inst_exc]: 2:2
- u_intr_state_cs_fatal_err: prim_subreg
Description
F[cs_fatal_err]: 3:3
- u_intr_enable_cs_cmd_req_done: prim_subreg
Description
R[intr_enable]: V(False)
F[cs_cmd_req_done]: 0:0
- u_intr_enable_cs_entropy_req: prim_subreg
Description
F[cs_entropy_req]: 1:1
- u_intr_enable_cs_hw_inst_exc: prim_subreg
Description
F[cs_hw_inst_exc]: 2:2
- u_intr_enable_cs_fatal_err: prim_subreg
Description
F[cs_fatal_err]: 3:3
- u_intr_test_cs_cmd_req_done: prim_subreg_ext
Description
R[intr_test]: V(True)
F[cs_cmd_req_done]: 0:0
- u_intr_test_cs_entropy_req: prim_subreg_ext
Description
F[cs_entropy_req]: 1:1
- u_intr_test_cs_hw_inst_exc: prim_subreg_ext
Description
F[cs_hw_inst_exc]: 2:2
- u_intr_test_cs_fatal_err: prim_subreg_ext
Description
F[cs_fatal_err]: 3:3
- u_alert_test_recov_alert: prim_subreg_ext
Description
R[alert_test]: V(True)
F[recov_alert]: 0:0
- u_alert_test_fatal_alert: prim_subreg_ext
Description
F[fatal_alert]: 1:1
- u_regwen: prim_subreg
Description
R[regwen]: V(False)
- u_ctrl_enable: prim_subreg
Description
R[ctrl]: V(False)
F[enable]: 3:0
- u_ctrl_sw_app_enable: prim_subreg
Description
F[sw_app_enable]: 7:4
- u_ctrl_read_int_state: prim_subreg
Description
F[read_int_state]: 11:8
- u_cmd_req: prim_subreg
Description
R[cmd_req]: V(False)
- u_sw_cmd_sts_cmd_rdy: prim_subreg
Description
R[sw_cmd_sts]: V(False)
F[cmd_rdy]: 0:0
- u_sw_cmd_sts_cmd_sts: prim_subreg
Description
F[cmd_sts]: 1:1
- u_genbits_vld_genbits_vld: prim_subreg_ext
Description
R[genbits_vld]: V(True)
F[genbits_vld]: 0:0
- u_genbits_vld_genbits_fips: prim_subreg_ext
Description
F[genbits_fips]: 1:1
- u_genbits: prim_subreg_ext
Description
R[genbits]: V(True)
- u_int_state_num: prim_subreg
Description
R[int_state_num]: V(False)
- u_int_state_val: prim_subreg_ext
Description
R[int_state_val]: V(True)
- u_hw_exc_sts: prim_subreg
Description
R[hw_exc_sts]: V(False)
- u_recov_alert_sts_enable_field_alert: prim_subreg
Description
R[recov_alert_sts]: V(False)
F[enable_field_alert]: 0:0
- u_recov_alert_sts_sw_app_enable_field_alert: prim_subreg
Description
F[sw_app_enable_field_alert]: 1:1
- u_recov_alert_sts_read_int_state_field_alert: prim_subreg
Description
F[read_int_state_field_alert]: 2:2
- u_err_code_sfifo_cmd_err: prim_subreg
Description
R[err_code]: V(False)
F[sfifo_cmd_err]: 0:0
- u_err_code_sfifo_genbits_err: prim_subreg
Description
F[sfifo_genbits_err]: 1:1
- u_err_code_sfifo_cmdreq_err: prim_subreg
Description
F[sfifo_cmdreq_err]: 2:2
- u_err_code_sfifo_rcstage_err: prim_subreg
Description
F[sfifo_rcstage_err]: 3:3
- u_err_code_sfifo_keyvrc_err: prim_subreg
Description
F[sfifo_keyvrc_err]: 4:4
- u_err_code_sfifo_updreq_err: prim_subreg
Description
F[sfifo_updreq_err]: 5:5
- u_err_code_sfifo_bencreq_err: prim_subreg
Description
F[sfifo_bencreq_err]: 6:6
- u_err_code_sfifo_bencack_err: prim_subreg
Description
F[sfifo_bencack_err]: 7:7
- u_err_code_sfifo_pdata_err: prim_subreg
Description
F[sfifo_pdata_err]: 8:8
- u_err_code_sfifo_final_err: prim_subreg
Description
F[sfifo_final_err]: 9:9
- u_err_code_sfifo_gbencack_err: prim_subreg
Description
F[sfifo_gbencack_err]: 10:10
- u_err_code_sfifo_grcstage_err: prim_subreg
Description
F[sfifo_grcstage_err]: 11:11
- u_err_code_sfifo_ggenreq_err: prim_subreg
Description
F[sfifo_ggenreq_err]: 12:12
- u_err_code_sfifo_gadstage_err: prim_subreg
Description
F[sfifo_gadstage_err]: 13:13
- u_err_code_sfifo_ggenbits_err: prim_subreg
Description
F[sfifo_ggenbits_err]: 14:14
- u_err_code_sfifo_blkenc_err: prim_subreg
Description
F[sfifo_blkenc_err]: 15:15
- u_err_code_cmd_stage_sm_err: prim_subreg
Description
F[cmd_stage_sm_err]: 20:20
- u_err_code_main_sm_err: prim_subreg
Description
F[main_sm_err]: 21:21
- u_err_code_drbg_gen_sm_err: prim_subreg
Description
F[drbg_gen_sm_err]: 22:22
- u_err_code_drbg_updbe_sm_err: prim_subreg
Description
F[drbg_updbe_sm_err]: 23:23
- u_err_code_drbg_updob_sm_err: prim_subreg
Description
F[drbg_updob_sm_err]: 24:24
- u_err_code_aes_cipher_sm_err: prim_subreg
Description
F[aes_cipher_sm_err]: 25:25
- u_err_code_fifo_write_err: prim_subreg
Description
F[fifo_write_err]: 28:28
- u_err_code_fifo_read_err: prim_subreg
Description
F[fifo_read_err]: 29:29
- u_err_code_fifo_state_err: prim_subreg
Description
F[fifo_state_err]: 30:30
- u_err_code_test: prim_subreg
Description
R[err_code_test]: V(False)
- u_sel_tracking_sm: prim_subreg
Description
R[sel_tracking_sm]: V(False)
- u_tracking_sm_obs_tracking_sm_obs0: prim_subreg
Description
R[tracking_sm_obs]: V(False)
F[tracking_sm_obs0]: 7:0
- u_tracking_sm_obs_tracking_sm_obs1: prim_subreg
Description
F[tracking_sm_obs1]: 15:8
- u_tracking_sm_obs_tracking_sm_obs2: prim_subreg
Description
F[tracking_sm_obs2]: 23:16
- u_tracking_sm_obs_tracking_sm_obs3: prim_subreg
Description
F[tracking_sm_obs3]: 31:24