Package: edn_reg_pkg
- File: edn_reg_pkg.sv
Description
Copyright lowRISC contributors.
Licensed under the Apache License, Version 2.0, see LICENSE for details.
SPDX-License-Identifier: Apache-2.0
Register Package auto-generated by reggen
containing data structure
Constants
Name | Type | Value | Description |
---|---|---|---|
NumAlerts | int | 2 | |
BlockAw | int | 6 | Address widths within the block |
BlockAw | logic [BlockAw-1:0] | undefined | Register offsets |
BlockAw | logic [BlockAw-1:0] | 4 | |
BlockAw | logic [BlockAw-1:0] | 8 | |
BlockAw | logic [BlockAw-1:0] | c | |
BlockAw | logic [BlockAw-1:0] | 10 | |
BlockAw | logic [BlockAw-1:0] | 14 | |
BlockAw | logic [BlockAw-1:0] | 18 | |
BlockAw | logic [BlockAw-1:0] | c | |
BlockAw | logic [BlockAw-1:0] | 20 | |
BlockAw | logic [BlockAw-1:0] | 24 | |
BlockAw | logic [BlockAw-1:0] | 28 | |
BlockAw | logic [BlockAw-1:0] | c | |
BlockAw | logic [BlockAw-1:0] | 30 | |
BlockAw | logic [BlockAw-1:0] | 34 | |
BlockAw | logic [BlockAw-1:0] | 38 | |
EDN_INTR_TEST_RESVAL | logic [1:0] | undefined | Reset values for hwext registers and their fields |
EDN_INTR_TEST_EDN_CMD_REQ_DONE_RESVAL | logic [0:0] | undefined | |
EDN_INTR_TEST_EDN_FATAL_ERR_RESVAL | logic [0:0] | undefined | |
EDN_ALERT_TEST_RESVAL | logic [1:0] | undefined | |
EDN_ALERT_TEST_RECOV_ALERT_RESVAL | logic [0:0] | undefined | |
EDN_ALERT_TEST_FATAL_ALERT_RESVAL | logic [0:0] | undefined | |
EDN_SW_CMD_REQ_RESVAL | logic [31:0] | undefined | |
EDN_RESEED_CMD_RESVAL | logic [31:0] | undefined | |
EDN_GENERATE_CMD_RESVAL | logic [31:0] | ||
EDN_PERMIT | logic [3:0] | undefined | Register width information to check illegal writes |
Types
Name | Type | Description |
---|---|---|
edn_reg2hw_intr_state_reg_t | struct packed { struct packed { logic q; } edn_cmd_req_done; struct packed { logic q; } edn_fatal_err; } |
////////////////////////// Typedefs for registers // ////////////////////////// |
edn_reg2hw_intr_enable_reg_t | struct packed { struct packed { logic q; } edn_cmd_req_done; struct packed { logic q; } edn_fatal_err; } |
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edn_reg2hw_intr_test_reg_t | struct packed { struct packed { logic q; logic qe; } edn_cmd_req_done; struct packed { logic q; logic qe; } edn_fatal_err; } |
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edn_reg2hw_alert_test_reg_t | struct packed { struct packed { logic q; logic qe; } recov_alert; struct packed { logic q; logic qe; } fatal_alert; } |
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edn_reg2hw_ctrl_reg_t | struct packed { struct packed { logic [3:0] q; } edn_enable; struct packed { logic [3:0] q; } boot_req_mode; struct packed { logic [3:0] q; } auto_req_mode; struct packed { logic [3:0] q; } cmd_fifo_rst; } |
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edn_reg2hw_sw_cmd_req_reg_t | struct packed { logic [31:0] q; logic qe; } |
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edn_reg2hw_reseed_cmd_reg_t | struct packed { logic [31:0] q; logic qe; } |
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edn_reg2hw_generate_cmd_reg_t | struct packed { logic [31:0] q; logic qe; } |
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edn_reg2hw_max_num_reqs_between_reseeds_reg_t | struct packed { logic [31:0] q; logic qe; } |
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edn_reg2hw_err_code_test_reg_t | struct packed { logic [4:0] q; logic qe; } |
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edn_hw2reg_intr_state_reg_t | struct packed { struct packed { logic d; logic de; } edn_cmd_req_done; struct packed { logic d; logic de; } edn_fatal_err; } |
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edn_hw2reg_sum_sts_reg_t | struct packed { struct packed { logic d; logic de; } req_mode_sm_sts; struct packed { logic d; logic de; } boot_inst_ack; } |
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edn_hw2reg_sw_cmd_sts_reg_t | struct packed { struct packed { logic d; logic de; } cmd_rdy; struct packed { logic d; logic de; } cmd_sts; } |
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edn_hw2reg_recov_alert_sts_reg_t | struct packed { logic d; logic de; } |
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edn_hw2reg_err_code_reg_t | struct packed { struct packed { logic d; logic de; } sfifo_rescmd_err; struct packed { logic d; logic de; } sfifo_gencmd_err; struct packed { logic d; logic de; } edn_ack_sm_err; struct packed { logic d; logic de; } edn_main_sm_err; struct packed { logic d; logic de; } fifo_write_err; struct packed { logic d; logic de; } fifo_read_err; struct packed { logic d; logic de; } fifo_state_err; } |
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edn_reg2hw_t | struct packed { edn_reg2hw_intr_state_reg_t intr_state; edn_reg2hw_intr_enable_reg_t intr_enable; edn_reg2hw_intr_test_reg_t intr_test; edn_reg2hw_alert_test_reg_t alert_test; edn_reg2hw_ctrl_reg_t ctrl; edn_reg2hw_sw_cmd_req_reg_t sw_cmd_req; edn_reg2hw_reseed_cmd_reg_t reseed_cmd; edn_reg2hw_generate_cmd_reg_t generate_cmd; edn_reg2hw_max_num_reqs_between_reseeds_reg_t max_num_reqs_between_reseeds; edn_reg2hw_err_code_test_reg_t err_code_test; } |
Register -> HW type |
edn_hw2reg_t | struct packed { edn_hw2reg_intr_state_reg_t intr_state; edn_hw2reg_sum_sts_reg_t sum_sts; edn_hw2reg_sw_cmd_sts_reg_t sw_cmd_sts; edn_hw2reg_recov_alert_sts_reg_t recov_alert_sts; edn_hw2reg_err_code_reg_t err_code; } |
HW -> register type |