Entity: edn_reg_top

File: edn_reg_top.sv

Diagram

Description

Copyright lowRISC contributors. Licensed under the Apache License, Version 2.0, see LICENSE for details. SPDX-License-Identifier: Apache-2.0

Ports

Port name	Direction	Description
clk_i	input
rst_ni	input
tl_i	input
tl_o	output
reg2hw	output	Write
hw2reg	input	Read
intg_err_o	output	Integrity check errors
devmode_i	input	If 1, explicit error return for unmapped register access

Signals

Name	Type	Description
reg_we	logic	register signals
reg_re	logic
reg_addr	logic [AW-1:0]
reg_wdata	logic [DW-1:0]
reg_be	logic [DBW-1:0]
reg_rdata	logic [DW-1:0]
reg_error	logic
addrmiss	logic
wr_err	logic
reg_rdata_next	logic [DW-1:0]
reg_busy	logic
tl_reg_h2d	tlul_pkg::tl_h2d_t
tl_reg_d2h	tlul_pkg::tl_d2h_t
intg_err	logic	incoming payload check
intg_err_q	logic
tl_o_pre	tlul_pkg::tl_d2h_t	outgoing integrity generation
intr_state_we	logic	Define SW related signals Format: {wd
intr_state_edn_cmd_req_done_qs	logic
intr_state_edn_cmd_req_done_wd	logic
intr_state_edn_fatal_err_qs	logic
intr_state_edn_fatal_err_wd	logic
intr_enable_we	logic
intr_enable_edn_cmd_req_done_qs	logic
intr_enable_edn_cmd_req_done_wd	logic
intr_enable_edn_fatal_err_qs	logic
intr_enable_edn_fatal_err_wd	logic
intr_test_we	logic
intr_test_edn_cmd_req_done_wd	logic
intr_test_edn_fatal_err_wd	logic
alert_test_we	logic
alert_test_recov_alert_wd	logic
alert_test_fatal_alert_wd	logic
regwen_we	logic
regwen_qs	logic
regwen_wd	logic
ctrl_we	logic
ctrl_edn_enable_qs	logic [3:0]
ctrl_edn_enable_wd	logic [3:0]
ctrl_boot_req_mode_qs	logic [3:0]
ctrl_boot_req_mode_wd	logic [3:0]
ctrl_auto_req_mode_qs	logic [3:0]
ctrl_auto_req_mode_wd	logic [3:0]
ctrl_cmd_fifo_rst_qs	logic [3:0]
ctrl_cmd_fifo_rst_wd	logic [3:0]
sum_sts_we	logic
sum_sts_req_mode_sm_sts_qs	logic
sum_sts_req_mode_sm_sts_wd	logic
sum_sts_boot_inst_ack_qs	logic
sum_sts_boot_inst_ack_wd	logic
sw_cmd_req_we	logic
sw_cmd_req_wd	logic [31:0]
sw_cmd_sts_cmd_rdy_qs	logic
sw_cmd_sts_cmd_sts_qs	logic
reseed_cmd_we	logic
reseed_cmd_wd	logic [31:0]
generate_cmd_we	logic
generate_cmd_wd	logic [31:0]
max_num_reqs_between_reseeds_we	logic
max_num_reqs_between_reseeds_qs	logic [31:0]
max_num_reqs_between_reseeds_wd	logic [31:0]
recov_alert_sts_we	logic
recov_alert_sts_qs	logic
recov_alert_sts_wd	logic
err_code_sfifo_rescmd_err_qs	logic
err_code_sfifo_gencmd_err_qs	logic
err_code_edn_ack_sm_err_qs	logic
err_code_edn_main_sm_err_qs	logic
err_code_fifo_write_err_qs	logic
err_code_fifo_read_err_qs	logic
err_code_fifo_state_err_qs	logic
err_code_test_we	logic
err_code_test_qs	logic [4:0]
err_code_test_wd	logic [4:0]
addr_hit	logic [14:0]
shadow_busy	logic	shadow busy
reg_busy_sel	logic	register busy
unused_wdata	logic	Unused signal tieoff wdata / byte enable are not always fully used add a blanket unused statement to handle lint waivers
unused_be	logic

Constants

Name	Type	Value	Description
AW	int	6
DW	int	32
DBW	int	DW/8	Byte Width

Processes

unnamed: ( @(posedge clk_i or negedge rst_ni) )

Type: always_ff

unnamed: ( )

Type: always_comb

unnamed: ( )

Type: always_comb

Description
Check sub-word write is permitted

unnamed: ( )

Type: always_comb

Description
Read data return

unnamed: ( )

Type: always_comb

Instantiations

u_chk: tlul_cmd_intg_chk

u_rsp_intg_gen: tlul_rsp_intg_gen

u_reg_if: tlul_adapter_reg

u_intr_state_edn_cmd_req_done: prim_subreg

Description
Register instances
R[intr_state]: V(False)
F[edn_cmd_req_done]: 0:0

u_intr_state_edn_fatal_err: prim_subreg

Description
F[edn_fatal_err]: 1:1

u_intr_enable_edn_cmd_req_done: prim_subreg

Description
R[intr_enable]: V(False)
F[edn_cmd_req_done]: 0:0

u_intr_enable_edn_fatal_err: prim_subreg

Description
F[edn_fatal_err]: 1:1

u_intr_test_edn_cmd_req_done: prim_subreg_ext

Description
R[intr_test]: V(True)
F[edn_cmd_req_done]: 0:0

u_intr_test_edn_fatal_err: prim_subreg_ext

Description
F[edn_fatal_err]: 1:1

u_alert_test_recov_alert: prim_subreg_ext

Description
R[alert_test]: V(True)
F[recov_alert]: 0:0

u_alert_test_fatal_alert: prim_subreg_ext

Description
F[fatal_alert]: 1:1

u_regwen: prim_subreg

Description
R[regwen]: V(False)

u_ctrl_edn_enable: prim_subreg

Description
R[ctrl]: V(False)
F[edn_enable]: 3:0

u_ctrl_boot_req_mode: prim_subreg

Description
F[boot_req_mode]: 7:4

u_ctrl_auto_req_mode: prim_subreg

Description
F[auto_req_mode]: 11:8

u_ctrl_cmd_fifo_rst: prim_subreg

Description
F[cmd_fifo_rst]: 15:12

u_sum_sts_req_mode_sm_sts: prim_subreg

Description
R[sum_sts]: V(False)
F[req_mode_sm_sts]: 0:0

u_sum_sts_boot_inst_ack: prim_subreg

Description
F[boot_inst_ack]: 1:1

u_sw_cmd_req: prim_subreg_ext

Description
R[sw_cmd_req]: V(True)

u_sw_cmd_sts_cmd_rdy: prim_subreg

Description
R[sw_cmd_sts]: V(False)
F[cmd_rdy]: 0:0

u_sw_cmd_sts_cmd_sts: prim_subreg

Description
F[cmd_sts]: 1:1

u_reseed_cmd: prim_subreg_ext

Description
R[reseed_cmd]: V(True)

u_generate_cmd: prim_subreg_ext

Description
R[generate_cmd]: V(True)

u_max_num_reqs_between_reseeds: prim_subreg

Description
R[max_num_reqs_between_reseeds]: V(False)

u_recov_alert_sts: prim_subreg

Description
R[recov_alert_sts]: V(False)

u_err_code_sfifo_rescmd_err: prim_subreg

Description
R[err_code]: V(False)
F[sfifo_rescmd_err]: 0:0

u_err_code_sfifo_gencmd_err: prim_subreg

Description
F[sfifo_gencmd_err]: 1:1

u_err_code_edn_ack_sm_err: prim_subreg

Description
F[edn_ack_sm_err]: 20:20

u_err_code_edn_main_sm_err: prim_subreg

Description
F[edn_main_sm_err]: 21:21

u_err_code_fifo_write_err: prim_subreg

Description
F[fifo_write_err]: 28:28

u_err_code_fifo_read_err: prim_subreg

Description
F[fifo_read_err]: 29:29

u_err_code_fifo_state_err: prim_subreg

Description
F[fifo_state_err]: 30:30

u_err_code_test: prim_subreg

Description
R[err_code_test]: V(False)