Entity: entropy_src_reg_top

File: entropy_src_reg_top.sv

Diagram

Description

Copyright lowRISC contributors. Licensed under the Apache License, Version 2.0, see LICENSE for details. SPDX-License-Identifier: Apache-2.0

Ports

Port name	Direction	Description
clk_i	input
rst_ni	input
tl_i	input
tl_o	output
reg2hw	output	Write
hw2reg	input	Read
intg_err_o	output	Integrity check errors
devmode_i	input	If 1, explicit error return for unmapped register access

Signals

Name	Type	Description
reg_we	logic	register signals
reg_re	logic
reg_addr	logic [AW-1:0]
reg_wdata	logic [DW-1:0]
reg_be	logic [DBW-1:0]
reg_rdata	logic [DW-1:0]
reg_error	logic
addrmiss	logic
wr_err	logic
reg_rdata_next	logic [DW-1:0]
reg_busy	logic
tl_reg_h2d	tlul_pkg::tl_h2d_t
tl_reg_d2h	tlul_pkg::tl_d2h_t
intg_err	logic	incoming payload check
intg_err_q	logic
tl_o_pre	tlul_pkg::tl_d2h_t	outgoing integrity generation
intr_state_we	logic	Define SW related signals Format: {wd
intr_state_es_entropy_valid_qs	logic
intr_state_es_entropy_valid_wd	logic
intr_state_es_health_test_failed_qs	logic
intr_state_es_health_test_failed_wd	logic
intr_state_es_observe_fifo_ready_qs	logic
intr_state_es_observe_fifo_ready_wd	logic
intr_state_es_fatal_err_qs	logic
intr_state_es_fatal_err_wd	logic
intr_enable_we	logic
intr_enable_es_entropy_valid_qs	logic
intr_enable_es_entropy_valid_wd	logic
intr_enable_es_health_test_failed_qs	logic
intr_enable_es_health_test_failed_wd	logic
intr_enable_es_observe_fifo_ready_qs	logic
intr_enable_es_observe_fifo_ready_wd	logic
intr_enable_es_fatal_err_qs	logic
intr_enable_es_fatal_err_wd	logic
intr_test_we	logic
intr_test_es_entropy_valid_wd	logic
intr_test_es_health_test_failed_wd	logic
intr_test_es_observe_fifo_ready_wd	logic
intr_test_es_fatal_err_wd	logic
alert_test_we	logic
alert_test_recov_alert_wd	logic
alert_test_fatal_alert_wd	logic
regwen_re	logic
regwen_qs	logic
rev_abi_revision_qs	logic [7:0]
rev_hw_revision_qs	logic [7:0]
rev_chip_type_qs	logic [7:0]
conf_we	logic
conf_enable_qs	logic [1:0]
conf_enable_wd	logic [1:0]
conf_boot_bypass_disable_qs	logic
conf_boot_bypass_disable_wd	logic
conf_repcnt_disable_qs	logic
conf_repcnt_disable_wd	logic
conf_adaptp_disable_qs	logic
conf_adaptp_disable_wd	logic
conf_bucket_disable_qs	logic
conf_bucket_disable_wd	logic
conf_markov_disable_qs	logic
conf_markov_disable_wd	logic
conf_health_test_clr_qs	logic
conf_health_test_clr_wd	logic
conf_rng_bit_en_qs	logic
conf_rng_bit_en_wd	logic
conf_rng_bit_sel_qs	logic [1:0]
conf_rng_bit_sel_wd	logic [1:0]
conf_extht_enable_qs	logic
conf_extht_enable_wd	logic
conf_repcnts_disable_qs	logic
conf_repcnts_disable_wd	logic
rate_we	logic
rate_qs	logic [15:0]
rate_wd	logic [15:0]
entropy_control_we	logic
entropy_control_es_route_qs	logic
entropy_control_es_route_wd	logic
entropy_control_es_type_qs	logic
entropy_control_es_type_wd	logic
entropy_data_re	logic
entropy_data_qs	logic [31:0]
health_test_windows_we	logic
health_test_windows_fips_window_qs	logic [15:0]
health_test_windows_fips_window_wd	logic [15:0]
health_test_windows_bypass_window_qs	logic [15:0]
health_test_windows_bypass_window_wd	logic [15:0]
repcnt_thresholds_re	logic
repcnt_thresholds_we	logic
repcnt_thresholds_fips_thresh_qs	logic [15:0]
repcnt_thresholds_fips_thresh_wd	logic [15:0]
repcnt_thresholds_bypass_thresh_qs	logic [15:0]
repcnt_thresholds_bypass_thresh_wd	logic [15:0]
repcnts_thresholds_re	logic
repcnts_thresholds_we	logic
repcnts_thresholds_fips_thresh_qs	logic [15:0]
repcnts_thresholds_fips_thresh_wd	logic [15:0]
repcnts_thresholds_bypass_thresh_qs	logic [15:0]
repcnts_thresholds_bypass_thresh_wd	logic [15:0]
adaptp_hi_thresholds_re	logic
adaptp_hi_thresholds_we	logic
adaptp_hi_thresholds_fips_thresh_qs	logic [15:0]
adaptp_hi_thresholds_fips_thresh_wd	logic [15:0]
adaptp_hi_thresholds_bypass_thresh_qs	logic [15:0]
adaptp_hi_thresholds_bypass_thresh_wd	logic [15:0]
adaptp_lo_thresholds_re	logic
adaptp_lo_thresholds_we	logic
adaptp_lo_thresholds_fips_thresh_qs	logic [15:0]
adaptp_lo_thresholds_fips_thresh_wd	logic [15:0]
adaptp_lo_thresholds_bypass_thresh_qs	logic [15:0]
adaptp_lo_thresholds_bypass_thresh_wd	logic [15:0]
bucket_thresholds_re	logic
bucket_thresholds_we	logic
bucket_thresholds_fips_thresh_qs	logic [15:0]
bucket_thresholds_fips_thresh_wd	logic [15:0]
bucket_thresholds_bypass_thresh_qs	logic [15:0]
bucket_thresholds_bypass_thresh_wd	logic [15:0]
markov_hi_thresholds_re	logic
markov_hi_thresholds_we	logic
markov_hi_thresholds_fips_thresh_qs	logic [15:0]
markov_hi_thresholds_fips_thresh_wd	logic [15:0]
markov_hi_thresholds_bypass_thresh_qs	logic [15:0]
markov_hi_thresholds_bypass_thresh_wd	logic [15:0]
markov_lo_thresholds_re	logic
markov_lo_thresholds_we	logic
markov_lo_thresholds_fips_thresh_qs	logic [15:0]
markov_lo_thresholds_fips_thresh_wd	logic [15:0]
markov_lo_thresholds_bypass_thresh_qs	logic [15:0]
markov_lo_thresholds_bypass_thresh_wd	logic [15:0]
extht_hi_thresholds_re	logic
extht_hi_thresholds_we	logic
extht_hi_thresholds_fips_thresh_qs	logic [15:0]
extht_hi_thresholds_fips_thresh_wd	logic [15:0]
extht_hi_thresholds_bypass_thresh_qs	logic [15:0]
extht_hi_thresholds_bypass_thresh_wd	logic [15:0]
extht_lo_thresholds_re	logic
extht_lo_thresholds_we	logic
extht_lo_thresholds_fips_thresh_qs	logic [15:0]
extht_lo_thresholds_fips_thresh_wd	logic [15:0]
extht_lo_thresholds_bypass_thresh_qs	logic [15:0]
extht_lo_thresholds_bypass_thresh_wd	logic [15:0]
repcnt_hi_watermarks_re	logic
repcnt_hi_watermarks_fips_watermark_qs	logic [15:0]
repcnt_hi_watermarks_bypass_watermark_qs	logic [15:0]
repcnts_hi_watermarks_re	logic
repcnts_hi_watermarks_fips_watermark_qs	logic [15:0]
repcnts_hi_watermarks_bypass_watermark_qs	logic [15:0]
adaptp_hi_watermarks_re	logic
adaptp_hi_watermarks_fips_watermark_qs	logic [15:0]
adaptp_hi_watermarks_bypass_watermark_qs	logic [15:0]
adaptp_lo_watermarks_re	logic
adaptp_lo_watermarks_fips_watermark_qs	logic [15:0]
adaptp_lo_watermarks_bypass_watermark_qs	logic [15:0]
extht_hi_watermarks_re	logic
extht_hi_watermarks_fips_watermark_qs	logic [15:0]
extht_hi_watermarks_bypass_watermark_qs	logic [15:0]
extht_lo_watermarks_re	logic
extht_lo_watermarks_fips_watermark_qs	logic [15:0]
extht_lo_watermarks_bypass_watermark_qs	logic [15:0]
bucket_hi_watermarks_re	logic
bucket_hi_watermarks_fips_watermark_qs	logic [15:0]
bucket_hi_watermarks_bypass_watermark_qs	logic [15:0]
markov_hi_watermarks_re	logic
markov_hi_watermarks_fips_watermark_qs	logic [15:0]
markov_hi_watermarks_bypass_watermark_qs	logic [15:0]
markov_lo_watermarks_re	logic
markov_lo_watermarks_fips_watermark_qs	logic [15:0]
markov_lo_watermarks_bypass_watermark_qs	logic [15:0]
repcnt_total_fails_re	logic
repcnt_total_fails_qs	logic [31:0]
repcnts_total_fails_re	logic
repcnts_total_fails_qs	logic [31:0]
adaptp_hi_total_fails_re	logic
adaptp_hi_total_fails_qs	logic [31:0]
adaptp_lo_total_fails_re	logic
adaptp_lo_total_fails_qs	logic [31:0]
bucket_total_fails_re	logic
bucket_total_fails_qs	logic [31:0]
markov_hi_total_fails_re	logic
markov_hi_total_fails_qs	logic [31:0]
markov_lo_total_fails_re	logic
markov_lo_total_fails_qs	logic [31:0]
extht_hi_total_fails_re	logic
extht_hi_total_fails_qs	logic [31:0]
extht_lo_total_fails_re	logic
extht_lo_total_fails_qs	logic [31:0]
alert_threshold_we	logic
alert_threshold_alert_threshold_qs	logic [15:0]
alert_threshold_alert_threshold_wd	logic [15:0]
alert_threshold_alert_threshold_inv_qs	logic [15:0]
alert_threshold_alert_threshold_inv_wd	logic [15:0]
alert_summary_fail_counts_re	logic
alert_summary_fail_counts_qs	logic [15:0]
alert_fail_counts_re	logic
alert_fail_counts_repcnt_fail_count_qs	logic [3:0]
alert_fail_counts_adaptp_hi_fail_count_qs	logic [3:0]
alert_fail_counts_adaptp_lo_fail_count_qs	logic [3:0]
alert_fail_counts_bucket_fail_count_qs	logic [3:0]
alert_fail_counts_markov_hi_fail_count_qs	logic [3:0]
alert_fail_counts_markov_lo_fail_count_qs	logic [3:0]
alert_fail_counts_repcnts_fail_count_qs	logic [3:0]
extht_fail_counts_re	logic
extht_fail_counts_extht_hi_fail_count_qs	logic [3:0]
extht_fail_counts_extht_lo_fail_count_qs	logic [3:0]
fw_ov_control_we	logic
fw_ov_control_fw_ov_mode_qs	logic
fw_ov_control_fw_ov_mode_wd	logic
fw_ov_control_fw_ov_entropy_insert_qs	logic
fw_ov_control_fw_ov_entropy_insert_wd	logic
fw_ov_rd_data_re	logic
fw_ov_rd_data_qs	logic [31:0]
fw_ov_wr_data_we	logic
fw_ov_wr_data_wd	logic [31:0]
observe_fifo_thresh_we	logic
observe_fifo_thresh_qs	logic [6:0]
observe_fifo_thresh_wd	logic [6:0]
debug_status_re	logic
debug_status_entropy_fifo_depth_qs	logic [2:0]
debug_status_sha3_fsm_qs	logic [2:0]
debug_status_sha3_block_pr_qs	logic
debug_status_sha3_squeezing_qs	logic
debug_status_sha3_absorbed_qs	logic
debug_status_sha3_err_qs	logic
debug_status_main_sm_idle_qs	logic
debug_status_main_sm_state_qs	logic [7:0]
seed_we	logic
seed_qs	logic [3:0]
seed_wd	logic [3:0]
recov_alert_sts_we	logic
recov_alert_sts_es_main_sm_alert_qs	logic
recov_alert_sts_es_main_sm_alert_wd	logic
recov_alert_sts_es_bus_cmp_alert_qs	logic
recov_alert_sts_es_bus_cmp_alert_wd	logic
err_code_sfifo_esrng_err_qs	logic
err_code_sfifo_observe_err_qs	logic
err_code_sfifo_esfinal_err_qs	logic
err_code_es_ack_sm_err_qs	logic
err_code_es_main_sm_err_qs	logic
err_code_fifo_write_err_qs	logic
err_code_fifo_read_err_qs	logic
err_code_fifo_state_err_qs	logic
err_code_test_we	logic
err_code_test_qs	logic [4:0]
err_code_test_wd	logic [4:0]
addr_hit	logic [50:0]
shadow_busy	logic	shadow busy
reg_busy_sel	logic	register busy
unused_wdata	logic	Unused signal tieoff wdata / byte enable are not always fully used add a blanket unused statement to handle lint waivers
unused_be	logic

Constants

Name	Type	Value	Description
AW	int	8
DW	int	32
DBW	int	DW/8	Byte Width

Processes

unnamed: ( @(posedge clk_i or negedge rst_ni) )

Type: always_ff

unnamed: ( )

Type: always_comb

unnamed: ( )

Type: always_comb

Description
Check sub-word write is permitted

unnamed: ( )

Type: always_comb

Description
Read data return

unnamed: ( )

Type: always_comb

Instantiations

u_chk: tlul_cmd_intg_chk

u_rsp_intg_gen: tlul_rsp_intg_gen

u_reg_if: tlul_adapter_reg

u_intr_state_es_entropy_valid: prim_subreg

Description
Register instances
R[intr_state]: V(False)
F[es_entropy_valid]: 0:0

u_intr_state_es_health_test_failed: prim_subreg

Description
F[es_health_test_failed]: 1:1

u_intr_state_es_observe_fifo_ready: prim_subreg

Description
F[es_observe_fifo_ready]: 2:2

u_intr_state_es_fatal_err: prim_subreg

Description
F[es_fatal_err]: 3:3

u_intr_enable_es_entropy_valid: prim_subreg

Description
R[intr_enable]: V(False)
F[es_entropy_valid]: 0:0

u_intr_enable_es_health_test_failed: prim_subreg

Description
F[es_health_test_failed]: 1:1

u_intr_enable_es_observe_fifo_ready: prim_subreg

Description
F[es_observe_fifo_ready]: 2:2

u_intr_enable_es_fatal_err: prim_subreg

Description
F[es_fatal_err]: 3:3

u_intr_test_es_entropy_valid: prim_subreg_ext

Description
R[intr_test]: V(True)
F[es_entropy_valid]: 0:0

u_intr_test_es_health_test_failed: prim_subreg_ext

Description
F[es_health_test_failed]: 1:1

u_intr_test_es_observe_fifo_ready: prim_subreg_ext

Description
F[es_observe_fifo_ready]: 2:2

u_intr_test_es_fatal_err: prim_subreg_ext

Description
F[es_fatal_err]: 3:3

u_alert_test_recov_alert: prim_subreg_ext

Description
R[alert_test]: V(True)
F[recov_alert]: 0:0

u_alert_test_fatal_alert: prim_subreg_ext

Description
F[fatal_alert]: 1:1

u_regwen: prim_subreg_ext

Description
R[regwen]: V(True)

u_conf_enable: prim_subreg

Description
R[conf]: V(False)
F[enable]: 1:0

u_conf_boot_bypass_disable: prim_subreg

Description
F[boot_bypass_disable]: 3:3

u_conf_repcnt_disable: prim_subreg

Description
F[repcnt_disable]: 4:4

u_conf_adaptp_disable: prim_subreg

Description
F[adaptp_disable]: 5:5

u_conf_bucket_disable: prim_subreg

Description
F[bucket_disable]: 6:6

u_conf_markov_disable: prim_subreg

Description
F[markov_disable]: 7:7

u_conf_health_test_clr: prim_subreg

Description
F[health_test_clr]: 8:8

u_conf_rng_bit_en: prim_subreg

Description
F[rng_bit_en]: 9:9

u_conf_rng_bit_sel: prim_subreg

Description
F[rng_bit_sel]: 11:10

u_conf_extht_enable: prim_subreg

Description
F[extht_enable]: 12:12

u_conf_repcnts_disable: prim_subreg

Description
F[repcnts_disable]: 13:13

u_rate: prim_subreg

Description
R[rate]: V(False)

u_entropy_control_es_route: prim_subreg

Description
R[entropy_control]: V(False)
F[es_route]: 0:0

u_entropy_control_es_type: prim_subreg

Description
F[es_type]: 1:1

u_entropy_data: prim_subreg_ext

Description
R[entropy_data]: V(True)

u_health_test_windows_fips_window: prim_subreg

Description
R[health_test_windows]: V(False)
F[fips_window]: 15:0

u_health_test_windows_bypass_window: prim_subreg

Description
F[bypass_window]: 31:16

u_repcnt_thresholds_fips_thresh: prim_subreg_ext

Description
R[repcnt_thresholds]: V(True)
F[fips_thresh]: 15:0

u_repcnt_thresholds_bypass_thresh: prim_subreg_ext