Package: flash_ctrl_pkg

Description

Copyright lowRISC contributors.
Licensed under the Apache License, Version 2.0, see LICENSE for details.
SPDX-License-Identifier: Apache-2.0

Flash Controller module.

Constants

Name Type Value Description
TL_AW logic [top_pkg::TL_AW-1:0] 'h20100000
NumBanks int unsigned flash_ctrl_reg_pkg::RegNumBanks design parameters that can be altered through topgen
PagesPerBank int unsigned flash_ctrl_reg_pkg::RegPagesPerBank
BusPgmResBytes int unsigned flash_ctrl_reg_pkg::RegBusPgmResBytes
DataWidth int 64 fixed parameters of flash derived from topgen parameters
MetaDataWidth int 12
InfoTypes int 3 How many types of info per bank
InfoTypeSize int undefined The following hard-wired values are there to work-around verilator. For some reason if the values are assigned through parameters verilator thinks they are not constant
InfosPerBank int undefined
WordsPerPage int 256 Number of flash words per page
BusWidth int top_pkg::TL_DW
MpRegions int 8 flash controller protection regions
FifoDepth int 16 rd / prog fifos
InfoTypesWidth int prim_util_pkg::vbits(InfoTypes)
DataByteWidth int prim_util_pkg::vbits(DataWidth / 8 flash phy parameters
BankW int prim_util_pkg::vbits(NumBanks)
InfoPageW int prim_util_pkg::vbits(InfosPerBank)
PageW int prim_util_pkg::vbits(PagesPerBank)
WordW int prim_util_pkg::vbits(WordsPerPage)
AddrW int BankW + PageW + WordW all flash range
BankAddrW int PageW + WordW 1 bank of flash range
AllPagesW int BankW + PageW
BusBytes int BusWidth / 8 flash ctrl / bus parameters flash / bus width may be different from actual flash word width
BusByteWidth int prim_util_pkg::vbits(BusBytes)
WidthMultiple int DataWidth / BusWidth
BusPgmRes int BusPgmResBytes / BusBytes Number of bus words that can be programmed at once
BusPgmResWidth int prim_util_pkg::vbits(BusPgmRes)
BusWordsPerPage int WordsPerPage * WidthMultiple
BusWordW int prim_util_pkg::vbits(BusWordsPerPage)
BusAddrW int BankW + PageW + BusWordW
BusBankAddrW int PageW + BusWordW
PhyAddrStart int BusWordW - WordW
FifoDepthW int prim_util_pkg::vbits(FifoDepth+1 fifo parameters
PageW logic [PageW-1:0] undefined The end address in bus words for each kind of partition in each bank
SeedWidth int 256 ////////////////////////// All memory protection, seed related parameters Those related for seed pages should be template candidates ////////////////////////// parameters for connected components
KeyWidth int 128
EdnWidth int edn_pkg::ENDPOINT_BUS_WIDTH
LfsrWidth int 32 Default Lfsr configurations These LFSR parameters have been generated with $ util/design/gen-lfsr-seed.py --width 32 --seed 1274809145 --prefix ""
lfsr_seed_t lfsr_seed_t 32'ha8cee782
lfsr_perm_t lfsr_perm_t
NumSeeds int 2 flash life cycle / key manager management constants One page for creator seeds One page for owner seeds One page for isolated flash page
BankW bit [BankW-1:0] 0
InfoTypesWidth bit [InfoTypesWidth-1:0] 0
CreatorSeedIdx bit [0:0] 0
OwnerSeedIdx bit [0:0] 1
PageW bit [PageW-1:0] 1
PageW bit [PageW-1:0] 2
PageW bit [PageW-1:0] 3
HwInfoRules int 5 hardware interface memory protection rules
HwDataRules int 1
info_page_cfg_t info_page_cfg_t undefined
info_page_cfg_t info_page_cfg_t undefined
HwInfoPageAttr info_page_attr_t undefined
flash_key_t flash_key_t 128'h5d707f8a2d01d400928fa691c6a6e0a4 ////////////////////////// Design time constants //////////////////////////
flash_key_t flash_key_t 128'h39953618f2ca6f674af39f64975ea1f5
ProgTypes int 2
FLASH_REQ_DEFAULT flash_req_t default value of flash_req_t (for dangling ports)
FLASH_RSP_DEFAULT flash_rsp_t default value of flash_rsp_t (for dangling ports)
WipeEntries int 5 entries to be wiped
RmaWipeEntries rma_wipe_entry_t flash_ctrl_pkg

Types

Name Type Description
flash_key_t logic [KeyWidth-1:0]
lfsr_seed_t logic [LfsrWidth-1:0]
lfsr_perm_t logic [LfsrWidth-1:0][$clog2(LfsrWidth)-1:0]
flash_lcmgr_phase_e enum logic [1:0] {
PhaseSeed,
PhaseRma,
PhaseNone,
PhaseInvalid }		 These LFSR parameters have been generated with $ util/design/gen-lfsr-seed.py --width 64 --seed 691876113 --prefix "" lcmgr phase enum
info_page_cfg_t flash_ctrl_reg_pkg::flash_ctrl_reg2hw_bank0_info0_page_cfg_mreg_t alias for super long reg_pkg typedef
mp_region_cfg_t flash_ctrl_reg_pkg::flash_ctrl_reg2hw_mp_region_cfg_mreg_t
page_addr_t struct packed {
logic [InfoTypesWidth-1:0] sel;
logic [AllPagesW-1:0] addr;
}		 memory protection specific structs
info_page_attr_t struct packed {
page_addr_t page;
flash_lcmgr_phase_e phase;
info_page_cfg_t cfg;
}
data_region_attr_t struct packed {
flash_lcmgr_phase_e phase;
mp_region_cfg_t cfg;
}
flash_op_e enum logic [1:0] {
FlashOpRead = 2'h0,
FlashOpProgram = 2'h1,
FlashOpErase = 2'h2,
FlashOpInvalid = 2'h3 }		 ////////////////////////// Flash operation related enums ////////////////////////// Flash Operations Supported
flash_prog_e enum logic {
FlashProgNormal = 0,
FlashProgRepair = 1 }		 Flash Program Operations Supported
flash_erase_e enum logic {
FlashErasePage = 0,
FlashEraseBank = 1 }		 Flash Erase Operations Supported
flash_sel_e enum logic [1:0] {
NoneSel,
SwSel,
HwSel }		 Flash function select
flash_flfo_dir_e enum logic {
WriteDir = 1'b0,
ReadDir = 1'b1 }		 Flash tlul to fifo direction
flash_part_e enum logic {
FlashPartData = 1'b0,
FlashPartInfo = 1'b1 }		 Flash partition type
mp_region_cfg_t struct packed {
logic req;
logic scramble_en;
logic ecc_en;
logic he_en;
logic rd_buf_en;
logic ecc_multi_err_en;
logic rd;
logic prog;
logic pg_erase;
logic bk_erase;
logic erase_suspend;
flash_part_e part;
logic [InfoTypesWidth-1:0] info_sel;
logic [BusAddrW-1:0] addr;
logic [BusWidth-1:0] prog_data;
logic prog_last;
flash_prog_e prog_type;
mp_region_cfg_t [MpRegions:0] region_cfgs;
logic [KeyWidth-1:0] addr_key;
logic [KeyWidth-1:0] data_key;
logic [KeyWidth-1:0] rand_addr_key;
logic [KeyWidth-1:0] rand_data_key;
logic alert_trig;
logic alert_ack;
jtag_pkg::jtag_req_t jtag_req;
logic intg_err;
lc_ctrl_pkg::lc_tx_t flash_disable;
}		 Flash controller to memory