Package: flash_ctrl_reg_pkg

Description

Copyright lowRISC contributors.
Licensed under the Apache License, Version 2.0, see LICENSE for details.
SPDX-License-Identifier: Apache-2.0

Register Package auto-generated by reggen containing data structure

Constants

Name Type Value Description
RegNumBanks int 2
RegPagesPerBank int 256
RegBusPgmResBytes int 512
RegPageWidth int 8
RegBankWidth int 1
NumRegions int 8
NumInfos0 int 10
NumInfos1 int 1
NumInfos2 int 2
WordsPerPage int 256
BytesPerWord int 8
BytesPerPage int 2048
BytesPerBank int 524288
NumAlerts int 4
CoreAw int 9 Address widths within the block
PrimAw int 1
MemAw int 1
CoreAw logic [CoreAw-1:0] undefined Register offsets for core interface
CoreAw logic [CoreAw-1:0] 4
CoreAw logic [CoreAw-1:0] 8
CoreAw logic [CoreAw-1:0] c
CoreAw logic [CoreAw-1:0] 10
CoreAw logic [CoreAw-1:0] 14
CoreAw logic [CoreAw-1:0] 18
CoreAw logic [CoreAw-1:0] c
CoreAw logic [CoreAw-1:0] 20
CoreAw logic [CoreAw-1:0] 24
CoreAw logic [CoreAw-1:0] 28
CoreAw logic [CoreAw-1:0] c
CoreAw logic [CoreAw-1:0] 30
CoreAw logic [CoreAw-1:0] 34
CoreAw logic [CoreAw-1:0] 38
CoreAw logic [CoreAw-1:0] c
CoreAw logic [CoreAw-1:0] 40
CoreAw logic [CoreAw-1:0] 44
CoreAw logic [CoreAw-1:0] 48
CoreAw logic [CoreAw-1:0] c
CoreAw logic [CoreAw-1:0] 50
CoreAw logic [CoreAw-1:0] 54
CoreAw logic [CoreAw-1:0] 58
CoreAw logic [CoreAw-1:0] c
CoreAw logic [CoreAw-1:0] 60
CoreAw logic [CoreAw-1:0] 64
CoreAw logic [CoreAw-1:0] 68
CoreAw logic [CoreAw-1:0] c
CoreAw logic [CoreAw-1:0] 70
CoreAw logic [CoreAw-1:0] 74
CoreAw logic [CoreAw-1:0] 78
CoreAw logic [CoreAw-1:0] c
CoreAw logic [CoreAw-1:0] 80
CoreAw logic [CoreAw-1:0] 84
CoreAw logic [CoreAw-1:0] 88
CoreAw logic [CoreAw-1:0] c
CoreAw logic [CoreAw-1:0] 90
CoreAw logic [CoreAw-1:0] 94
CoreAw logic [CoreAw-1:0] 98
CoreAw logic [CoreAw-1:0] c
CoreAw logic [CoreAw-1:0] a0
CoreAw logic [CoreAw-1:0] a4
CoreAw logic [CoreAw-1:0] a8
CoreAw logic [CoreAw-1:0] ac
CoreAw logic [CoreAw-1:0] b0
CoreAw logic [CoreAw-1:0] b4
CoreAw logic [CoreAw-1:0] b8
CoreAw logic [CoreAw-1:0] bc
CoreAw logic [CoreAw-1:0] c0
CoreAw logic [CoreAw-1:0] c4
CoreAw logic [CoreAw-1:0] c8
CoreAw logic [CoreAw-1:0] cc
CoreAw logic [CoreAw-1:0] d0
CoreAw logic [CoreAw-1:0] d4
CoreAw logic [CoreAw-1:0] d8
CoreAw logic [CoreAw-1:0] dc
CoreAw logic [CoreAw-1:0] e0
CoreAw logic [CoreAw-1:0] e4
CoreAw logic [CoreAw-1:0] e8
CoreAw logic [CoreAw-1:0] ec
CoreAw logic [CoreAw-1:0] f0
CoreAw logic [CoreAw-1:0] f4
CoreAw logic [CoreAw-1:0] f8
CoreAw logic [CoreAw-1:0] fc
CoreAw logic [CoreAw-1:0] 100
CoreAw logic [CoreAw-1:0] 104
CoreAw logic [CoreAw-1:0] 108
CoreAw logic [CoreAw-1:0] c
CoreAw logic [CoreAw-1:0] 110
CoreAw logic [CoreAw-1:0] 114
CoreAw logic [CoreAw-1:0] 118
CoreAw logic [CoreAw-1:0] c
CoreAw logic [CoreAw-1:0] 120
CoreAw logic [CoreAw-1:0] 124
CoreAw logic [CoreAw-1:0] 128
CoreAw logic [CoreAw-1:0] c
CoreAw logic [CoreAw-1:0] 130
CoreAw logic [CoreAw-1:0] 134
CoreAw logic [CoreAw-1:0] 138
CoreAw logic [CoreAw-1:0] c
CoreAw logic [CoreAw-1:0] 140
CoreAw logic [CoreAw-1:0] 144
CoreAw logic [CoreAw-1:0] 148
CoreAw logic [CoreAw-1:0] c
CoreAw logic [CoreAw-1:0] 150
CoreAw logic [CoreAw-1:0] 154
CoreAw logic [CoreAw-1:0] 158
CoreAw logic [CoreAw-1:0] c
CoreAw logic [CoreAw-1:0] 160
CoreAw logic [CoreAw-1:0] 164
CoreAw logic [CoreAw-1:0] 168
CoreAw logic [CoreAw-1:0] c
CoreAw logic [CoreAw-1:0] 170
CoreAw logic [CoreAw-1:0] 174
CoreAw logic [CoreAw-1:0] 178
CoreAw logic [CoreAw-1:0] c
CoreAw logic [CoreAw-1:0] 180
CoreAw logic [CoreAw-1:0] 184
CoreAw logic [CoreAw-1:0] 188
CoreAw logic [CoreAw-1:0] c
FLASH_CTRL_INTR_TEST_RESVAL logic [5:0] undefined Reset values for hwext registers and their fields for core interface
FLASH_CTRL_INTR_TEST_PROG_EMPTY_RESVAL logic [0:0] undefined
FLASH_CTRL_INTR_TEST_PROG_LVL_RESVAL logic [0:0] undefined
FLASH_CTRL_INTR_TEST_RD_FULL_RESVAL logic [0:0] undefined
FLASH_CTRL_INTR_TEST_RD_LVL_RESVAL logic [0:0] undefined
FLASH_CTRL_INTR_TEST_OP_DONE_RESVAL logic [0:0] undefined
FLASH_CTRL_INTR_TEST_ERR_RESVAL logic [0:0] undefined
FLASH_CTRL_ALERT_TEST_RESVAL logic [3:0] undefined
FLASH_CTRL_ALERT_TEST_RECOV_ERR_RESVAL logic [0:0] undefined
FLASH_CTRL_ALERT_TEST_RECOV_MP_ERR_RESVAL logic [0:0] undefined
FLASH_CTRL_ALERT_TEST_RECOV_ECC_ERR_RESVAL logic [0:0] undefined
FLASH_CTRL_ALERT_TEST_FATAL_INTG_ERR_RESVAL logic [0:0] undefined
FLASH_CTRL_CTRL_REGWEN_RESVAL logic [0:0] undefined
FLASH_CTRL_CTRL_REGWEN_EN_RESVAL logic [0:0] logic [CoreAw-1:0]
FLASH_CTRL_PROG_FIFO_SIZE int unsigned 4
CoreAw logic [CoreAw-1:0] 194
FLASH_CTRL_RD_FIFO_SIZE int unsigned 4
FLASH_CTRL_CORE_PERMIT logic [3:0] undefined Register width information to check illegal writes for core interface

Types

Name Type Description
flash_ctrl_reg2hw_intr_state_reg_t struct packed {
struct packed {
logic q;
} prog_empty;
struct packed {
logic q;
} prog_lvl;
struct packed {
logic q;
} rd_full;
struct packed {
logic q;
} rd_lvl;
struct packed {
logic q;
} op_done;
struct packed {
logic q;
} err;
}		 ///////////////////////////////////////////// Typedefs for registers for core interface // /////////////////////////////////////////////
flash_ctrl_reg2hw_intr_enable_reg_t struct packed {
struct packed {
logic q;
} prog_empty;
struct packed {
logic q;
} prog_lvl;
struct packed {
logic q;
} rd_full;
struct packed {
logic q;
} rd_lvl;
struct packed {
logic q;
} op_done;
struct packed {
logic q;
} err;
}
flash_ctrl_reg2hw_intr_test_reg_t struct packed {
struct packed {
logic q;
logic qe;
} prog_empty;
struct packed {
logic q;
logic qe;
} prog_lvl;
struct packed {
logic q;
logic qe;
} rd_full;
struct packed {
logic q;
logic qe;
} rd_lvl;
struct packed {
logic q;
logic qe;
} op_done;
struct packed {
logic q;
logic qe;
} err;
}
flash_ctrl_reg2hw_alert_test_reg_t struct packed {
struct packed {
logic q;
logic qe;
} recov_err;
struct packed {
logic q;
logic qe;
} recov_mp_err;
struct packed {
logic q;
logic qe;
} recov_ecc_err;
struct packed {
logic q;
logic qe;
} fatal_intg_err;
}
flash_ctrl_reg2hw_flash_disable_reg_t struct packed {
logic q;
}
flash_ctrl_reg2hw_init_reg_t struct packed {
logic q;
}
flash_ctrl_reg2hw_control_reg_t struct packed {
struct packed {
logic q;
} start;
struct packed {
logic [1:0] q;
} op;
struct packed {
logic q;
} prog_sel;
struct packed {
logic q;
} erase_sel;
struct packed {
logic q;
} partition_sel;
struct packed {
logic [1:0] q;
} info_sel;
struct packed {
logic [11:0] q;
} num;
}
flash_ctrl_reg2hw_addr_reg_t struct packed {
logic [31:0] q;
}
flash_ctrl_reg2hw_prog_type_en_reg_t struct packed {
struct packed {
logic q;
} normal;
struct packed {
logic q;
} repair;
}
flash_ctrl_reg2hw_erase_suspend_reg_t struct packed {
logic q;
}
flash_ctrl_reg2hw_mp_region_cfg_mreg_t struct packed {
struct packed {
logic q;
} en;
struct packed {
logic q;
} rd_en;
struct packed {
logic q;
} prog_en;
struct packed {
logic q;
} erase_en;
struct packed {
logic q;
} scramble_en;
struct packed {
logic q;
} ecc_en;
struct packed {
logic q;
} he_en;
struct packed {
logic [8:0] q;
} base;
struct packed {
logic [9:0] q;
} size;
}
flash_ctrl_reg2hw_default_region_reg_t struct packed {
struct packed {
logic q;
} rd_en;
struct packed {
logic q;
} prog_en;
struct packed {
logic q;
} erase_en;
struct packed {
logic q;
} scramble_en;
struct packed {
logic q;
} ecc_en;
struct packed {
logic q;
} he_en;
}
flash_ctrl_reg2hw_bank0_info0_page_cfg_mreg_t struct packed {
struct packed {
logic q;
} en;
struct packed {
logic q;
} rd_en;
struct packed {
logic q;
} prog_en;
struct packed {
logic q;
} erase_en;
struct packed {
logic q;
} scramble_en;
struct packed {
logic q;
} ecc_en;
struct packed {
logic q;
} he_en;
}
flash_ctrl_reg2hw_bank0_info1_page_cfg_mreg_t struct packed {
struct packed {
logic q;
} en;
struct packed {
logic q;
} rd_en;
struct packed {
logic q;
} prog_en;
struct packed {
logic q;
} erase_en;
struct packed {
logic q;
} scramble_en;
struct packed {
logic q;
} ecc_en;
struct packed {
logic q;
} he_en;
}
flash_ctrl_reg2hw_bank0_info2_page_cfg_mreg_t struct packed {
struct packed {
logic q;
} en;
struct packed {
logic q;
} rd_en;
struct packed {
logic q;
} prog_en;
struct packed {
logic q;
} erase_en;
struct packed {
logic q;
} scramble_en;
struct packed {
logic q;
} ecc_en;
struct packed {
logic q;
} he_en;
}
flash_ctrl_reg2hw_bank1_info0_page_cfg_mreg_t struct packed {
struct packed {
logic q;
} en;
struct packed {
logic q;
} rd_en;
struct packed {
logic q;
} prog_en;
struct packed {
logic q;
} erase_en;
struct packed {
logic q;
} scramble_en;
struct packed {
logic q;
} ecc_en;
struct packed {
logic q;
} he_en;
}
flash_ctrl_reg2hw_bank1_info1_page_cfg_mreg_t struct packed {
struct packed {
logic q;
} en;
struct packed {
logic q;
} rd_en;
struct packed {
logic q;
} prog_en;
struct packed {
logic q;
} erase_en;
struct packed {
logic q;
} scramble_en;
struct packed {
logic q;
} ecc_en;
struct packed {
logic q;
} he_en;
}
flash_ctrl_reg2hw_bank1_info2_page_cfg_mreg_t struct packed {
struct packed {
logic q;
} en;
struct packed {
logic q;
} rd_en;
struct packed {
logic q;
} prog_en;
struct packed {
logic q;
} erase_en;
struct packed {
logic q;
} scramble_en;
struct packed {
logic q;
} ecc_en;
struct packed {
logic q;
} he_en;
}
flash_ctrl_reg2hw_mp_bank_cfg_mreg_t struct packed {
logic q;
}
flash_ctrl_reg2hw_err_code_intr_en_reg_t struct packed {
struct packed {
logic q;
} flash_err_en;
struct packed {
logic q;
} flash_alert_en;
struct packed {
logic q;
} oob_err;
struct packed {
logic q;
} mp_err;
struct packed {
logic q;
} ecc_single_err;
struct packed {
logic q;
} ecc_multi_err;
}
flash_ctrl_reg2hw_err_code_reg_t struct packed {
struct packed {
logic q;
} flash_err;
struct packed {
logic q;
} flash_alert;
struct packed {
logic q;
} oob_err;
struct packed {
logic q;
} mp_err;
struct packed {
logic q;
} ecc_single_err;
struct packed {
logic q;
} ecc_multi_err;
}
flash_ctrl_reg2hw_ecc_single_err_cnt_reg_t struct packed {
logic [7:0] q;
}
flash_ctrl_reg2hw_ecc_multi_err_cnt_reg_t struct packed {
logic [7:0] q;
}
flash_ctrl_reg2hw_phy_err_cfg_reg_t struct packed {
logic q;
}
flash_ctrl_reg2hw_phy_alert_cfg_reg_t struct packed {
struct packed {
logic q;
} alert_ack;
struct packed {
logic q;
} alert_trig;
}
flash_ctrl_reg2hw_scratch_reg_t struct packed {
logic [31:0] q;
}
flash_ctrl_reg2hw_fifo_lvl_reg_t struct packed {
struct packed {
logic [4:0] q;
} prog;
struct packed {
logic [4:0] q;
} rd;
}
flash_ctrl_reg2hw_fifo_rst_reg_t struct packed {
logic q;
}
flash_ctrl_hw2reg_intr_state_reg_t struct packed {
struct packed {
logic d;
logic de;
} prog_empty;
struct packed {
logic d;
logic de;
} prog_lvl;
struct packed {
logic d;
logic de;
} rd_full;
struct packed {
logic d;
logic de;
} rd_lvl;
struct packed {
logic d;
logic de;
} op_done;
struct packed {
logic d;
logic de;
} err;
}
flash_ctrl_hw2reg_ctrl_regwen_reg_t struct packed {
logic d;
}
flash_ctrl_hw2reg_control_reg_t struct packed {
struct packed {
logic d;
logic de;
} start;
}
flash_ctrl_hw2reg_erase_suspend_reg_t struct packed {
logic d;
logic de;
}
flash_ctrl_hw2reg_op_status_reg_t struct packed {
struct packed {
logic d;
logic de;
} done;
struct packed {
logic d;
logic de;
} err;
}
flash_ctrl_hw2reg_status_reg_t struct packed {
struct packed {
logic d;
logic de;
} rd_full;
struct packed {
logic d;
logic de;
} rd_empty;
struct packed {
logic d;
logic de;
} prog_full;
struct packed {
logic d;
logic de;
} prog_empty;
struct packed {
logic d;
logic de;
} init_wip;
}
flash_ctrl_hw2reg_err_code_reg_t struct packed {
struct packed {
logic d;
logic de;
} flash_err;
struct packed {
logic d;
logic de;
} flash_alert;
struct packed {
logic d;
logic de;
} oob_err;
struct packed {
logic d;
logic de;
} mp_err;
struct packed {
logic d;
logic de;
} ecc_single_err;
struct packed {
logic d;
logic de;
} ecc_multi_err;
}
flash_ctrl_hw2reg_err_addr_reg_t struct packed {
logic [8:0] d;
logic de;
}
flash_ctrl_hw2reg_ecc_single_err_cnt_reg_t struct packed {
logic [7:0] d;
logic de;
}
flash_ctrl_hw2reg_ecc_single_err_addr_mreg_t struct packed {
logic [19:0] d;
logic de;
}
flash_ctrl_hw2reg_ecc_multi_err_cnt_reg_t struct packed {
logic [7:0] d;
logic de;
}
flash_ctrl_hw2reg_ecc_multi_err_addr_mreg_t struct packed {
logic [19:0] d;
logic de;
}
flash_ctrl_hw2reg_phy_status_reg_t struct packed {
struct packed {
logic d;
logic de;
} init_wip;
struct packed {
logic d;
logic de;
} prog_normal_avail;
struct packed {
logic d;
logic de;
} prog_repair_avail;
}
flash_ctrl_reg2hw_mp_region_cfg_mreg_t struct packed {
flash_ctrl_reg2hw_intr_state_reg_t intr_state;
flash_ctrl_reg2hw_intr_enable_reg_t intr_enable;
flash_ctrl_reg2hw_intr_test_reg_t intr_test;
flash_ctrl_reg2hw_alert_test_reg_t alert_test;
flash_ctrl_reg2hw_flash_disable_reg_t flash_disable;
flash_ctrl_reg2hw_init_reg_t init;
flash_ctrl_reg2hw_control_reg_t control;
flash_ctrl_reg2hw_addr_reg_t addr;
flash_ctrl_reg2hw_prog_type_en_reg_t prog_type_en;
flash_ctrl_reg2hw_erase_suspend_reg_t erase_suspend;
flash_ctrl_reg2hw_mp_region_cfg_mreg_t [7:0] mp_region_cfg;
flash_ctrl_reg2hw_default_region_reg_t default_region;
flash_ctrl_reg2hw_bank0_info0_page_cfg_mreg_t [9:0] bank0_info0_page_cfg;
flash_ctrl_reg2hw_bank0_info1_page_cfg_mreg_t [0:0] bank0_info1_page_cfg;
flash_ctrl_reg2hw_bank0_info2_page_cfg_mreg_t [1:0] bank0_info2_page_cfg;
flash_ctrl_reg2hw_bank1_info0_page_cfg_mreg_t [9:0] bank1_info0_page_cfg;
flash_ctrl_reg2hw_bank1_info1_page_cfg_mreg_t [0:0] bank1_info1_page_cfg;
flash_ctrl_reg2hw_bank1_info2_page_cfg_mreg_t [1:0] bank1_info2_page_cfg;
flash_ctrl_reg2hw_mp_bank_cfg_mreg_t [1:0] mp_bank_cfg;
flash_ctrl_reg2hw_err_code_intr_en_reg_t err_code_intr_en;
flash_ctrl_reg2hw_err_code_reg_t err_code;
flash_ctrl_reg2hw_ecc_single_err_cnt_reg_t ecc_single_err_cnt;
flash_ctrl_reg2hw_ecc_multi_err_cnt_reg_t ecc_multi_err_cnt;
flash_ctrl_reg2hw_phy_err_cfg_reg_t phy_err_cfg;
flash_ctrl_reg2hw_phy_alert_cfg_reg_t phy_alert_cfg;
flash_ctrl_reg2hw_scratch_reg_t scratch;
flash_ctrl_reg2hw_fifo_lvl_reg_t fifo_lvl;
flash_ctrl_reg2hw_fifo_rst_reg_t fifo_rst;
}		 Register -> HW type for core interface
flash_ctrl_hw2reg_ecc_single_err_addr_mreg_t struct packed {
flash_ctrl_hw2reg_intr_state_reg_t intr_state;
flash_ctrl_hw2reg_ctrl_regwen_reg_t ctrl_regwen;
flash_ctrl_hw2reg_control_reg_t control;
flash_ctrl_hw2reg_erase_suspend_reg_t erase_suspend;
flash_ctrl_hw2reg_op_status_reg_t op_status;
flash_ctrl_hw2reg_status_reg_t status;
flash_ctrl_hw2reg_err_code_reg_t err_code;
flash_ctrl_hw2reg_err_addr_reg_t err_addr;
flash_ctrl_hw2reg_ecc_single_err_cnt_reg_t ecc_single_err_cnt;
flash_ctrl_hw2reg_ecc_single_err_addr_mreg_t [1:0] ecc_single_err_addr;
flash_ctrl_hw2reg_ecc_multi_err_cnt_reg_t ecc_multi_err_cnt;
flash_ctrl_hw2reg_ecc_multi_err_addr_mreg_t [1:0] ecc_multi_err_addr;
flash_ctrl_hw2reg_phy_status_reg_t phy_status;
}		 HW -> register type for core interface
flash_ctrl_core_id_e enum int {
FLASH_CTRL_INTR_STATE,
FLASH_CTRL_INTR_ENABLE,
FLASH_CTRL_INTR_TEST,
FLASH_CTRL_ALERT_TEST,
FLASH_CTRL_FLASH_DISABLE,
FLASH_CTRL_INIT,
FLASH_CTRL_CTRL_REGWEN,
FLASH_CTRL_CONTROL,
FLASH_CTRL_ADDR,
FLASH_CTRL_PROG_TYPE_EN,
FLASH_CTRL_ERASE_SUSPEND,
FLASH_CTRL_REGION_CFG_REGWEN_0,
FLASH_CTRL_REGION_CFG_REGWEN_1,
FLASH_CTRL_REGION_CFG_REGWEN_2,
FLASH_CTRL_REGION_CFG_REGWEN_3,
FLASH_CTRL_REGION_CFG_REGWEN_4,
FLASH_CTRL_REGION_CFG_REGWEN_5,
FLASH_CTRL_REGION_CFG_REGWEN_6,
FLASH_CTRL_REGION_CFG_REGWEN_7,
FLASH_CTRL_MP_REGION_CFG_0,
FLASH_CTRL_MP_REGION_CFG_1,
FLASH_CTRL_MP_REGION_CFG_2,
FLASH_CTRL_MP_REGION_CFG_3,
FLASH_CTRL_MP_REGION_CFG_4,
FLASH_CTRL_MP_REGION_CFG_5,
FLASH_CTRL_MP_REGION_CFG_6,
FLASH_CTRL_MP_REGION_CFG_7,
FLASH_CTRL_DEFAULT_REGION,
FLASH_CTRL_BANK0_INFO0_REGWEN_0,
FLASH_CTRL_BANK0_INFO0_REGWEN_1,
FLASH_CTRL_BANK0_INFO0_REGWEN_2,
FLASH_CTRL_BANK0_INFO0_REGWEN_3,
FLASH_CTRL_BANK0_INFO0_REGWEN_4,
FLASH_CTRL_BANK0_INFO0_REGWEN_5,
FLASH_CTRL_BANK0_INFO0_REGWEN_6,
FLASH_CTRL_BANK0_INFO0_REGWEN_7,
FLASH_CTRL_BANK0_INFO0_REGWEN_8,
FLASH_CTRL_BANK0_INFO0_REGWEN_9,
FLASH_CTRL_BANK0_INFO0_PAGE_CFG_0,
FLASH_CTRL_BANK0_INFO0_PAGE_CFG_1,
FLASH_CTRL_BANK0_INFO0_PAGE_CFG_2,
FLASH_CTRL_BANK0_INFO0_PAGE_CFG_3,
FLASH_CTRL_BANK0_INFO0_PAGE_CFG_4,
FLASH_CTRL_BANK0_INFO0_PAGE_CFG_5,
FLASH_CTRL_BANK0_INFO0_PAGE_CFG_6,
FLASH_CTRL_BANK0_INFO0_PAGE_CFG_7,
FLASH_CTRL_BANK0_INFO0_PAGE_CFG_8,
FLASH_CTRL_BANK0_INFO0_PAGE_CFG_9,
FLASH_CTRL_BANK0_INFO1_REGWEN,
FLASH_CTRL_BANK0_INFO1_PAGE_CFG,
FLASH_CTRL_BANK0_INFO2_REGWEN_0,
FLASH_CTRL_BANK0_INFO2_REGWEN_1,
FLASH_CTRL_BANK0_INFO2_PAGE_CFG_0,
FLASH_CTRL_BANK0_INFO2_PAGE_CFG_1,
FLASH_CTRL_BANK1_INFO0_REGWEN_0,
FLASH_CTRL_BANK1_INFO0_REGWEN_1,
FLASH_CTRL_BANK1_INFO0_REGWEN_2,
FLASH_CTRL_BANK1_INFO0_REGWEN_3,
FLASH_CTRL_BANK1_INFO0_REGWEN_4,
FLASH_CTRL_BANK1_INFO0_REGWEN_5,
FLASH_CTRL_BANK1_INFO0_REGWEN_6,
FLASH_CTRL_BANK1_INFO0_REGWEN_7,
FLASH_CTRL_BANK1_INFO0_REGWEN_8,
FLASH_CTRL_BANK1_INFO0_REGWEN_9,
FLASH_CTRL_BANK1_INFO0_PAGE_CFG_0,
FLASH_CTRL_BANK1_INFO0_PAGE_CFG_1,
FLASH_CTRL_BANK1_INFO0_PAGE_CFG_2,
FLASH_CTRL_BANK1_INFO0_PAGE_CFG_3,
FLASH_CTRL_BANK1_INFO0_PAGE_CFG_4,
FLASH_CTRL_BANK1_INFO0_PAGE_CFG_5,
FLASH_CTRL_BANK1_INFO0_PAGE_CFG_6,
FLASH_CTRL_BANK1_INFO0_PAGE_CFG_7,
FLASH_CTRL_BANK1_INFO0_PAGE_CFG_8,
FLASH_CTRL_BANK1_INFO0_PAGE_CFG_9,
FLASH_CTRL_BANK1_INFO1_REGWEN,
FLASH_CTRL_BANK1_INFO1_PAGE_CFG,
FLASH_CTRL_BANK1_INFO2_REGWEN_0,
FLASH_CTRL_BANK1_INFO2_REGWEN_1,
FLASH_CTRL_BANK1_INFO2_PAGE_CFG_0,
FLASH_CTRL_BANK1_INFO2_PAGE_CFG_1,
FLASH_CTRL_BANK_CFG_REGWEN,
FLASH_CTRL_MP_BANK_CFG,
FLASH_CTRL_OP_STATUS,
FLASH_CTRL_STATUS,
FLASH_CTRL_ERR_CODE_INTR_EN,
FLASH_CTRL_ERR_CODE,
FLASH_CTRL_ERR_ADDR,
FLASH_CTRL_ECC_SINGLE_ERR_CNT,
FLASH_CTRL_ECC_SINGLE_ERR_ADDR_0,
FLASH_CTRL_ECC_SINGLE_ERR_ADDR_1,
FLASH_CTRL_ECC_MULTI_ERR_CNT,
FLASH_CTRL_ECC_MULTI_ERR_ADDR_0,
FLASH_CTRL_ECC_MULTI_ERR_ADDR_1,
FLASH_CTRL_PHY_ERR_CFG_REGWEN,
FLASH_CTRL_PHY_ERR_CFG,
FLASH_CTRL_PHY_ALERT_CFG,
FLASH_CTRL_PHY_STATUS,
FLASH_CTRL_SCRATCH,
FLASH_CTRL_FIFO_LVL,
FLASH_CTRL_FIFO_RST }		 Register index for core interface