Package: flash_phy_pkg

Description

Copyright lowRISC contributors.
Licensed under the Apache License, Version 2.0, see LICENSE for details.
SPDX-License-Identifier: Apache-2.0

Flash phy module package

Constants

Name Type Value Description
NumBanks int flash_ctrl_pkg::NumBanks
InfosPerBank int flash_ctrl_pkg::InfosPerBank
PagesPerBank int flash_ctrl_pkg::PagesPerBank
WordsPerPage int flash_ctrl_pkg::WordsPerPage
BankW int flash_ctrl_pkg::BankW
PageW int flash_ctrl_pkg::PageW
WordW int flash_ctrl_pkg::WordW
BankAddrW int flash_ctrl_pkg::BankAddrW
DataWidth int flash_ctrl_pkg::DataWidth
EccWidth int 8
MetaDataWidth int flash_ctrl_pkg::MetaDataWidth
WidthMultiple int flash_ctrl_pkg::WidthMultiple
NumBuf int 4 number of flash read buffers
RspOrderDepth int 2 this should be DataWidth / BusWidth
ScrDataWidth int DataWidth + EccWidth will switch to this after bus widening
FullDataWidth int DataWidth + MetaDataWidth
InfoTypes int flash_ctrl_pkg::InfoTypes
InfoTypesWidth int flash_ctrl_pkg::InfoTypesWidth
BusWidth int flash_ctrl_pkg::BusWidth flash ctrl / bus parameters
BusBankAddrW int flash_ctrl_pkg::BusBankAddrW
BusWordW int flash_ctrl_pkg::BusWordW
ProgTypes int flash_ctrl_pkg::ProgTypes
AddrBitsRemain int DataWidth % BusWidth address bits remain must be 0
LsbAddrBit int $clog2(WidthMultiple) base index This is the lsb position of the prim flash address when looking at the bus address
WordSelW int WidthMultiple == 1 ? 1 : LsbAddrBit
KeySize int 128 scramble / de-scramble parameters Number of cycles the gf_mult is given to complete
GfMultCycles int 2
CipherCycles int 2 If this value is greater than 1, constraints must be updated for multicycle paths
RspOrderFifoWidth int $bits(rsp_fifo_entry_t)
PhyOps int 4

Types

Name Type Description
rd_buf_attr_e enum logic [1:0] {
Invalid = 2'h0,
Wip = 2'h1,
Valid = 2'h2,
Undef = 2'h3 }		 Read buffer metadata
rd_buf_t struct packed {
logic [DataWidth-1:0] data;
logic [BankAddrW-1:0] addr;
logic part;
logic [InfoTypesWidth-1:0] info_sel;
rd_buf_attr_e attr;
}
rsp_fifo_entry_t struct packed {
logic [NumBuf-1:0] buf_sel;
logic [WordSelW-1:0] word_sel;
}
rd_attr_t struct packed {
logic [BankAddrW-1:0] addr;
logic descramble;
logic ecc;
tlul_pkg::tl_type_e req_type;
}
flash_phy_op_e enum logic [1:0] {
PhyRead = 2'h0,
PhyProg = 2'h1,
PhyPgErase = 2'h2,
PhyBkErase = 2'h3 }		 Flash Operations Supported
flash_phy_op_sel_e enum logic [1:0] {
None = 2'h0,
Host = 2'h1,
Ctrl = 2'h2 }		 Flash Operations Selected
cipher_ops_e enum logic {
ScrambleOp = 1'b0,
DeScrambleOp = 1'b1 }
flash_phy_prim_flash_req_t struct packed {
logic rd_req;
logic prog_req;
logic prog_last;
flash_ctrl_pkg::flash_prog_e prog_type;
logic pg_erase_req;
logic bk_erase_req;
logic erase_suspend_req;
logic he;
logic [BankAddrW-1:0] addr;
flash_ctrl_pkg::flash_part_e part;
logic [InfoTypesWidth-1:0] info_sel;
logic [FullDataWidth-1:0] prog_full_data;
}		 Connections to prim_flash
flash_phy_prim_flash_rsp_t struct packed {
logic ack;
logic done;
logic [FullDataWidth-1:0] rdata;
}