Entity: gpio_reg_top
- File: gpio_reg_top.sv
Diagram
Description
Copyright lowRISC contributors. Licensed under the Apache License, Version 2.0, see LICENSE for details. SPDX-License-Identifier: Apache-2.0
Register Top module auto-generated by reggen
Ports
| Port name | Direction | Type | Description |
|---|---|---|---|
| clk_i | input | ||
| rst_ni | input | ||
| tl_i | input | ||
| tl_o | output | ||
| reg2hw | output | Write | |
| hw2reg | input | Read | |
| intg_err_o | output | Integrity check errors | |
| devmode_i | input | If 1, explicit error return for unmapped register access |
Signals
| Name | Type | Description |
|---|---|---|
| reg_we | logic | register signals |
| reg_re | logic | |
| reg_addr | logic [AW-1:0] | |
| reg_wdata | logic [DW-1:0] | |
| reg_be | logic [DBW-1:0] | |
| reg_rdata | logic [DW-1:0] | |
| reg_error | logic | |
| addrmiss | logic | |
| wr_err | logic | |
| reg_rdata_next | logic [DW-1:0] | |
| reg_busy | logic | |
| tl_reg_h2d | tlul_pkg::tl_h2d_t | |
| tl_reg_d2h | tlul_pkg::tl_d2h_t | |
| intg_err | logic | incoming payload check |
| intg_err_q | logic | |
| tl_o_pre | tlul_pkg::tl_d2h_t | outgoing integrity generation |
| intr_state_we | logic | Define SW related signals Format: |
| intr_state_qs | logic [31:0] | |
| intr_state_wd | logic [31:0] | |
| intr_enable_we | logic | |
| intr_enable_qs | logic [31:0] | |
| intr_enable_wd | logic [31:0] | |
| intr_test_we | logic | |
| intr_test_wd | logic [31:0] | |
| alert_test_we | logic | |
| alert_test_wd | logic | |
| data_in_qs | logic [31:0] | |
| direct_out_re | logic | |
| direct_out_we | logic | |
| direct_out_qs | logic [31:0] | |
| direct_out_wd | logic [31:0] | |
| masked_out_lower_re | logic | |
| masked_out_lower_we | logic | |
| masked_out_lower_data_qs | logic [15:0] | |
| masked_out_lower_data_wd | logic [15:0] | |
| masked_out_lower_mask_wd | logic [15:0] | |
| masked_out_upper_re | logic | |
| masked_out_upper_we | logic | |
| masked_out_upper_data_qs | logic [15:0] | |
| masked_out_upper_data_wd | logic [15:0] | |
| masked_out_upper_mask_wd | logic [15:0] | |
| direct_oe_re | logic | |
| direct_oe_we | logic | |
| direct_oe_qs | logic [31:0] | |
| direct_oe_wd | logic [31:0] | |
| masked_oe_lower_re | logic | |
| masked_oe_lower_we | logic | |
| masked_oe_lower_data_qs | logic [15:0] | |
| masked_oe_lower_data_wd | logic [15:0] | |
| masked_oe_lower_mask_qs | logic [15:0] | |
| masked_oe_lower_mask_wd | logic [15:0] | |
| masked_oe_upper_re | logic | |
| masked_oe_upper_we | logic | |
| masked_oe_upper_data_qs | logic [15:0] | |
| masked_oe_upper_data_wd | logic [15:0] | |
| masked_oe_upper_mask_qs | logic [15:0] | |
| masked_oe_upper_mask_wd | logic [15:0] | |
| intr_ctrl_en_rising_we | logic | |
| intr_ctrl_en_rising_qs | logic [31:0] | |
| intr_ctrl_en_rising_wd | logic [31:0] | |
| intr_ctrl_en_falling_we | logic | |
| intr_ctrl_en_falling_qs | logic [31:0] | |
| intr_ctrl_en_falling_wd | logic [31:0] | |
| intr_ctrl_en_lvlhigh_we | logic | |
| intr_ctrl_en_lvlhigh_qs | logic [31:0] | |
| intr_ctrl_en_lvlhigh_wd | logic [31:0] | |
| intr_ctrl_en_lvllow_we | logic | |
| intr_ctrl_en_lvllow_qs | logic [31:0] | |
| intr_ctrl_en_lvllow_wd | logic [31:0] | |
| ctrl_en_input_filter_we | logic | |
| ctrl_en_input_filter_qs | logic [31:0] | |
| ctrl_en_input_filter_wd | logic [31:0] | |
| addr_hit | logic [15:0] | |
| shadow_busy | logic | shadow busy |
| reg_busy_sel | logic | register busy |
| unused_wdata | logic | Unused signal tieoff wdata / byte enable are not always fully used add a blanket unused statement to handle lint waivers |
| unused_be | logic |
Constants
| Name | Type | Value | Description |
|---|---|---|---|
| AW | int | 6 | |
| DW | int | 32 | |
| DBW | int | DW/8 | Byte Width |
Processes
- unnamed: ( @(posedge clk_i or negedge rst_ni) )
Type: always_ff
- unnamed: ( )
Type: always_comb
- unnamed: ( )
Type: always_comb
Description
Check sub-word write is permitted
- unnamed: ( )
Type: always_comb
Description
Read data return
- unnamed: ( )
Type: always_comb
Instantiations
- u_chk: tlul_cmd_intg_chk
- u_rsp_intg_gen: tlul_rsp_intg_gen
- u_reg_if: tlul_adapter_reg
- u_intr_state: prim_subreg
Description
Register instances
R[intr_state]: V(False)
- u_intr_enable: prim_subreg
Description
R[intr_enable]: V(False)
- u_intr_test: prim_subreg_ext
Description
R[intr_test]: V(True)
- u_alert_test: prim_subreg_ext
Description
R[alert_test]: V(True)
- u_data_in: prim_subreg
Description
R[data_in]: V(False)
- u_direct_out: prim_subreg_ext
Description
R[direct_out]: V(True)
- u_masked_out_lower_data: prim_subreg_ext
Description
R[masked_out_lower]: V(True)
F[data]: 15:0
- u_masked_out_lower_mask: prim_subreg_ext
Description
F[mask]: 31:16
- u_masked_out_upper_data: prim_subreg_ext
Description
R[masked_out_upper]: V(True)
F[data]: 15:0
- u_masked_out_upper_mask: prim_subreg_ext
Description
F[mask]: 31:16
- u_direct_oe: prim_subreg_ext
Description
R[direct_oe]: V(True)
- u_masked_oe_lower_data: prim_subreg_ext
Description
R[masked_oe_lower]: V(True)
F[data]: 15:0
- u_masked_oe_lower_mask: prim_subreg_ext
Description
F[mask]: 31:16
- u_masked_oe_upper_data: prim_subreg_ext
Description
R[masked_oe_upper]: V(True)
F[data]: 15:0
- u_masked_oe_upper_mask: prim_subreg_ext
Description
F[mask]: 31:16
- u_intr_ctrl_en_rising: prim_subreg
Description
R[intr_ctrl_en_rising]: V(False)
- u_intr_ctrl_en_falling: prim_subreg
Description
R[intr_ctrl_en_falling]: V(False)
- u_intr_ctrl_en_lvlhigh: prim_subreg
Description
R[intr_ctrl_en_lvlhigh]: V(False)
- u_intr_ctrl_en_lvllow: prim_subreg
Description
R[intr_ctrl_en_lvllow]: V(False)
- u_ctrl_en_input_filter: prim_subreg
Description
R[ctrl_en_input_filter]: V(False)