Package: hmac_reg_pkg
- File: hmac_reg_pkg.sv
Description
Copyright lowRISC contributors.
Licensed under the Apache License, Version 2.0, see LICENSE for details.
SPDX-License-Identifier: Apache-2.0
Register Package auto-generated by reggen containing data structure
Constants
| Name | Type | Value | Description |
|---|---|---|---|
| NumWords | int | 8 | |
| NumAlerts | int | 1 | |
| BlockAw | int | 12 | Address widths within the block |
| BlockAw | logic [BlockAw-1:0] | undefined | Register offsets |
| BlockAw | logic [BlockAw-1:0] | 4 | |
| BlockAw | logic [BlockAw-1:0] | 8 | |
| BlockAw | logic [BlockAw-1:0] | c | |
| BlockAw | logic [BlockAw-1:0] | 10 | |
| BlockAw | logic [BlockAw-1:0] | 14 | |
| BlockAw | logic [BlockAw-1:0] | 18 | |
| BlockAw | logic [BlockAw-1:0] | c | |
| BlockAw | logic [BlockAw-1:0] | 20 | |
| BlockAw | logic [BlockAw-1:0] | 24 | |
| BlockAw | logic [BlockAw-1:0] | 28 | |
| BlockAw | logic [BlockAw-1:0] | c | |
| BlockAw | logic [BlockAw-1:0] | 30 | |
| BlockAw | logic [BlockAw-1:0] | 34 | |
| BlockAw | logic [BlockAw-1:0] | 38 | |
| BlockAw | logic [BlockAw-1:0] | c | |
| BlockAw | logic [BlockAw-1:0] | 40 | |
| BlockAw | logic [BlockAw-1:0] | 44 | |
| BlockAw | logic [BlockAw-1:0] | 48 | |
| BlockAw | logic [BlockAw-1:0] | c | |
| BlockAw | logic [BlockAw-1:0] | 50 | |
| BlockAw | logic [BlockAw-1:0] | 54 | |
| BlockAw | logic [BlockAw-1:0] | 58 | |
| BlockAw | logic [BlockAw-1:0] | c | |
| BlockAw | logic [BlockAw-1:0] | 60 | |
| BlockAw | logic [BlockAw-1:0] | 64 | |
| BlockAw | logic [BlockAw-1:0] | 68 | |
| HMAC_INTR_TEST_RESVAL | logic [2:0] | undefined | Reset values for hwext registers and their fields |
| HMAC_INTR_TEST_HMAC_DONE_RESVAL | logic [0:0] | undefined | |
| HMAC_INTR_TEST_FIFO_EMPTY_RESVAL | logic [0:0] | undefined | |
| HMAC_INTR_TEST_HMAC_ERR_RESVAL | logic [0:0] | undefined | |
| HMAC_ALERT_TEST_RESVAL | logic [0:0] | undefined | |
| HMAC_ALERT_TEST_FATAL_FAULT_RESVAL | logic [0:0] | undefined | |
| HMAC_CFG_RESVAL | logic [3:0] | 4 | |
| HMAC_CFG_ENDIAN_SWAP_RESVAL | logic [0:0] | undefined | |
| HMAC_CFG_DIGEST_SWAP_RESVAL | logic [0:0] | undefined | |
| HMAC_CMD_RESVAL | logic [1:0] | undefined | |
| HMAC_STATUS_RESVAL | logic [8:0] | undefined | |
| HMAC_STATUS_FIFO_EMPTY_RESVAL | logic [0:0] | undefined | |
| HMAC_WIPE_SECRET_RESVAL | logic [31:0] | undefined | |
| HMAC_KEY_0_RESVAL | logic [31:0] | undefined | |
| HMAC_KEY_1_RESVAL | logic [31:0] | undefined | |
| HMAC_KEY_2_RESVAL | logic [31:0] | undefined | |
| HMAC_KEY_3_RESVAL | logic [31:0] | undefined | |
| HMAC_KEY_4_RESVAL | logic [31:0] | undefined | |
| HMAC_KEY_5_RESVAL | logic [31:0] | undefined | |
| HMAC_KEY_6_RESVAL | logic [31:0] | undefined | |
| HMAC_KEY_7_RESVAL | logic [31:0] | undefined | |
| HMAC_DIGEST_0_RESVAL | logic [31:0] | undefined | |
| HMAC_DIGEST_1_RESVAL | logic [31:0] | undefined | |
| HMAC_DIGEST_2_RESVAL | logic [31:0] | undefined | |
| HMAC_DIGEST_3_RESVAL | logic [31:0] | undefined | |
| HMAC_DIGEST_4_RESVAL | logic [31:0] | undefined | |
| HMAC_DIGEST_5_RESVAL | logic [31:0] | undefined | |
| HMAC_DIGEST_6_RESVAL | logic [31:0] | undefined | |
| HMAC_DIGEST_7_RESVAL | logic [31:0] | logic [BlockAw-1:0] | |
| HMAC_MSG_FIFO_SIZE | int unsigned | 800 | |
| HMAC_PERMIT | logic [3:0] | undefined | Register width information to check illegal writes |
Types
| Name | Type | Description |
|---|---|---|
| hmac_reg2hw_intr_state_reg_t | struct packed { struct packed { logic q; } hmac_done; struct packed { logic q; } fifo_empty; struct packed { logic q; } hmac_err; } |
////////////////////////// Typedefs for registers // ////////////////////////// |
| hmac_reg2hw_intr_enable_reg_t | struct packed { struct packed { logic q; } hmac_done; struct packed { logic q; } fifo_empty; struct packed { logic q; } hmac_err; } |
|
| hmac_reg2hw_intr_test_reg_t | struct packed { struct packed { logic q; logic qe; } hmac_done; struct packed { logic q; logic qe; } fifo_empty; struct packed { logic q; logic qe; } hmac_err; } |
|
| hmac_reg2hw_alert_test_reg_t | struct packed { logic q; logic qe; } |
|
| hmac_reg2hw_cfg_reg_t | struct packed { struct packed { logic q; logic qe; } hmac_en; struct packed { logic q; logic qe; } sha_en; struct packed { logic q; logic qe; } endian_swap; struct packed { logic q; logic qe; } digest_swap; } |
|
| hmac_reg2hw_cmd_reg_t | struct packed { struct packed { logic q; logic qe; } hash_start; struct packed { logic q; logic qe; } hash_process; } |
|
| hmac_reg2hw_wipe_secret_reg_t | struct packed { logic [31:0] q; logic qe; } |
|
| hmac_reg2hw_key_mreg_t | struct packed { logic [31:0] q; logic qe; } |
|
| hmac_hw2reg_intr_state_reg_t | struct packed { struct packed { logic d; logic de; } hmac_done; struct packed { logic d; logic de; } fifo_empty; struct packed { logic d; logic de; } hmac_err; } |
|
| hmac_hw2reg_cfg_reg_t | struct packed { struct packed { logic d; } hmac_en; struct packed { logic d; } sha_en; struct packed { logic d; } endian_swap; struct packed { logic d; } digest_swap; } |
|
| hmac_hw2reg_status_reg_t | struct packed { struct packed { logic d; } fifo_empty; struct packed { logic d; } fifo_full; struct packed { logic [4:0] d; } fifo_depth; } |
|
| hmac_hw2reg_err_code_reg_t | struct packed { logic [31:0] d; logic de; } |
|
| hmac_hw2reg_key_mreg_t | struct packed { logic [31:0] d; } |
|
| hmac_hw2reg_digest_mreg_t | struct packed { logic [31:0] d; } |
|
| hmac_hw2reg_msg_length_lower_reg_t | struct packed { logic [31:0] d; logic de; } |
|
| hmac_hw2reg_msg_length_upper_reg_t | struct packed { logic [31:0] d; logic de; } |
|
| hmac_reg2hw_key_mreg_t | struct packed { hmac_reg2hw_intr_state_reg_t intr_state; hmac_reg2hw_intr_enable_reg_t intr_enable; hmac_reg2hw_intr_test_reg_t intr_test; hmac_reg2hw_alert_test_reg_t alert_test; hmac_reg2hw_cfg_reg_t cfg; hmac_reg2hw_cmd_reg_t cmd; hmac_reg2hw_wipe_secret_reg_t wipe_secret; hmac_reg2hw_key_mreg_t [7:0] key; } |
Register -> HW type |
| hmac_hw2reg_key_mreg_t | struct packed { hmac_hw2reg_intr_state_reg_t intr_state; hmac_hw2reg_cfg_reg_t cfg; hmac_hw2reg_status_reg_t status; hmac_hw2reg_err_code_reg_t err_code; hmac_hw2reg_key_mreg_t [7:0] key; hmac_hw2reg_digest_mreg_t [7:0] digest; hmac_hw2reg_msg_length_lower_reg_t msg_length_lower; hmac_hw2reg_msg_length_upper_reg_t msg_length_upper; } |
HW -> register type |
| hmac_id_e | enum int { HMAC_INTR_STATE, HMAC_INTR_ENABLE, HMAC_INTR_TEST, HMAC_ALERT_TEST, HMAC_CFG, HMAC_CMD, HMAC_STATUS, HMAC_ERR_CODE, HMAC_WIPE_SECRET, HMAC_KEY_0, HMAC_KEY_1, HMAC_KEY_2, HMAC_KEY_3, HMAC_KEY_4, HMAC_KEY_5, HMAC_KEY_6, HMAC_KEY_7, HMAC_DIGEST_0, HMAC_DIGEST_1, HMAC_DIGEST_2, HMAC_DIGEST_3, HMAC_DIGEST_4, HMAC_DIGEST_5, HMAC_DIGEST_6, HMAC_DIGEST_7, HMAC_MSG_LENGTH_LOWER, HMAC_MSG_LENGTH_UPPER } |
Register index |