Entity: hmac_reg_top

File: hmac_reg_top.sv

Diagram

Description

Copyright lowRISC contributors. Licensed under the Apache License, Version 2.0, see LICENSE for details. SPDX-License-Identifier: Apache-2.0

Ports

Port name	Direction	Description
clk_i	input
rst_ni	input
tl_i	input
tl_o	output
tl_win_o	output	Output port for window
tl_win_i	input
reg2hw	output	Write
hw2reg	input	Read
intg_err_o	output	Integrity check errors
devmode_i	input	If 1, explicit error return for unmapped register access

Signals

Name	Type	Description
reg_we	logic	register signals
reg_re	logic
reg_addr	logic [AW-1:0]
reg_wdata	logic [DW-1:0]
reg_be	logic [DBW-1:0]
reg_rdata	logic [DW-1:0]
reg_error	logic
addrmiss	logic
wr_err	logic
reg_rdata_next	logic [DW-1:0]
reg_busy	logic
tl_reg_h2d	tlul_pkg::tl_h2d_t
tl_reg_d2h	tlul_pkg::tl_d2h_t
intg_err	logic	incoming payload check
intg_err_q	logic
tl_o_pre	tlul_pkg::tl_d2h_t	outgoing integrity generation
tl_socket_h2d	tlul_pkg::tl_h2d_t
tl_socket_d2h	tlul_pkg::tl_d2h_t
reg_steer	logic [1:0]
intr_state_we	logic	Define SW related signals Format: {wd
intr_state_hmac_done_qs	logic
intr_state_hmac_done_wd	logic
intr_state_fifo_empty_qs	logic
intr_state_fifo_empty_wd	logic
intr_state_hmac_err_qs	logic
intr_state_hmac_err_wd	logic
intr_enable_we	logic
intr_enable_hmac_done_qs	logic
intr_enable_hmac_done_wd	logic
intr_enable_fifo_empty_qs	logic
intr_enable_fifo_empty_wd	logic
intr_enable_hmac_err_qs	logic
intr_enable_hmac_err_wd	logic
intr_test_we	logic
intr_test_hmac_done_wd	logic
intr_test_fifo_empty_wd	logic
intr_test_hmac_err_wd	logic
alert_test_we	logic
alert_test_wd	logic
cfg_re	logic
cfg_we	logic
cfg_hmac_en_qs	logic
cfg_hmac_en_wd	logic
cfg_sha_en_qs	logic
cfg_sha_en_wd	logic
cfg_endian_swap_qs	logic
cfg_endian_swap_wd	logic
cfg_digest_swap_qs	logic
cfg_digest_swap_wd	logic
cmd_we	logic
cmd_hash_start_wd	logic
cmd_hash_process_wd	logic
status_re	logic
status_fifo_empty_qs	logic
status_fifo_full_qs	logic
status_fifo_depth_qs	logic [4:0]
err_code_qs	logic [31:0]
wipe_secret_we	logic
wipe_secret_wd	logic [31:0]
key_0_we	logic
key_0_wd	logic [31:0]
key_1_we	logic
key_1_wd	logic [31:0]
key_2_we	logic
key_2_wd	logic [31:0]
key_3_we	logic
key_3_wd	logic [31:0]
key_4_we	logic
key_4_wd	logic [31:0]
key_5_we	logic
key_5_wd	logic [31:0]
key_6_we	logic
key_6_wd	logic [31:0]
key_7_we	logic
key_7_wd	logic [31:0]
digest_0_re	logic
digest_0_qs	logic [31:0]
digest_1_re	logic
digest_1_qs	logic [31:0]
digest_2_re	logic
digest_2_qs	logic [31:0]
digest_3_re	logic
digest_3_qs	logic [31:0]
digest_4_re	logic
digest_4_qs	logic [31:0]
digest_5_re	logic
digest_5_qs	logic [31:0]
digest_6_re	logic
digest_6_qs	logic [31:0]
digest_7_re	logic
digest_7_qs	logic [31:0]
msg_length_lower_qs	logic [31:0]
msg_length_upper_qs	logic [31:0]
addr_hit	logic [26:0]
shadow_busy	logic	shadow busy
reg_busy_sel	logic	register busy
unused_wdata	logic	Unused signal tieoff wdata / byte enable are not always fully used add a blanket unused statement to handle lint waivers
unused_be	logic

Constants

Name	Type	Value	Description
AW	int	12
DW	int	32
DBW	int	DW/8	Byte Width

Processes

unnamed: ( @(posedge clk_i or negedge rst_ni) )

Type: always_ff

unnamed: ( )

Type: always_comb

Description
Create steering logic

unnamed: ( )

Type: always_comb

unnamed: ( )

Type: always_comb

Description
Check sub-word write is permitted

unnamed: ( )

Type: always_comb

Description
Read data return

unnamed: ( )

Type: always_comb

Instantiations

u_chk: tlul_cmd_intg_chk

u_rsp_intg_gen: tlul_rsp_intg_gen

u_socket: tlul_socket_1n

Description
Create Socket_1n

u_reg_if: tlul_adapter_reg

u_intr_state_hmac_done: prim_subreg

Description
Register instances
R[intr_state]: V(False)
F[hmac_done]: 0:0

u_intr_state_fifo_empty: prim_subreg

Description
F[fifo_empty]: 1:1

u_intr_state_hmac_err: prim_subreg

Description
F[hmac_err]: 2:2

u_intr_enable_hmac_done: prim_subreg

Description
R[intr_enable]: V(False)
F[hmac_done]: 0:0

u_intr_enable_fifo_empty: prim_subreg

Description
F[fifo_empty]: 1:1

u_intr_enable_hmac_err: prim_subreg

Description
F[hmac_err]: 2:2

u_intr_test_hmac_done: prim_subreg_ext

Description
R[intr_test]: V(True)
F[hmac_done]: 0:0

u_intr_test_fifo_empty: prim_subreg_ext

Description
F[fifo_empty]: 1:1

u_intr_test_hmac_err: prim_subreg_ext

Description
F[hmac_err]: 2:2

u_alert_test: prim_subreg_ext

Description
R[alert_test]: V(True)

u_cfg_hmac_en: prim_subreg_ext

Description
R[cfg]: V(True)
F[hmac_en]: 0:0

u_cfg_sha_en: prim_subreg_ext

Description
F[sha_en]: 1:1

u_cfg_endian_swap: prim_subreg_ext

Description
F[endian_swap]: 2:2

u_cfg_digest_swap: prim_subreg_ext

Description
F[digest_swap]: 3:3

u_cmd_hash_start: prim_subreg_ext

Description
R[cmd]: V(True)
F[hash_start]: 0:0

u_cmd_hash_process: prim_subreg_ext

Description
F[hash_process]: 1:1

u_status_fifo_empty: prim_subreg_ext

Description
R[status]: V(True)
F[fifo_empty]: 0:0

u_status_fifo_full: prim_subreg_ext

Description
F[fifo_full]: 1:1

u_status_fifo_depth: prim_subreg_ext

Description
F[fifo_depth]: 8:4

u_err_code: prim_subreg

Description
R[err_code]: V(False)

u_wipe_secret: prim_subreg_ext

Description
R[wipe_secret]: V(True)

u_msg_length_lower: prim_subreg

Description
R[msg_length_lower]: V(False)

u_msg_length_upper: prim_subreg

Description
R[msg_length_upper]: V(False)