Entity: lc_ctrl_reg_top

• File: lc_ctrl_reg_top.sv

Diagram

Description

Ports

Port name	Direction	Type	Description
clk_i	input
rst_ni	input
tl_i	input
tl_o	output
reg2hw	output		Write
hw2reg	input		Read
intg_err_o	output		Integrity check errors
devmode_i	input		If 1, explicit error return for unmapped register access

Signals

Name	Type	Description
reg_we	logic	register signals
reg_re	logic
reg_addr	logic [AW-1:0]
reg_wdata	logic [DW-1:0]
reg_be	logic [DBW-1:0]
reg_rdata	logic [DW-1:0]
reg_error	logic
addrmiss	logic
wr_err	logic
reg_rdata_next	logic [DW-1:0]
reg_busy	logic
tl_reg_h2d	tlul_pkg::tl_h2d_t
tl_reg_d2h	tlul_pkg::tl_d2h_t
intg_err	logic	incoming payload check
intg_err_q	logic
tl_o_pre	tlul_pkg::tl_d2h_t	outgoing integrity generation
alert_test_we	logic	Define SW related signals Format: {wd
alert_test_fatal_prog_error_wd	logic
alert_test_fatal_state_error_wd	logic
alert_test_fatal_bus_integ_error_wd	logic
status_re	logic
status_ready_qs	logic
status_transition_successful_qs	logic
status_transition_count_error_qs	logic
status_transition_error_qs	logic
status_token_error_qs	logic
status_flash_rma_error_qs	logic
status_otp_error_qs	logic
status_state_error_qs	logic
status_bus_integ_error_qs	logic
status_otp_partition_error_qs	logic
claim_transition_if_re	logic
claim_transition_if_we	logic
claim_transition_if_qs	logic [7:0]
claim_transition_if_wd	logic [7:0]
transition_regwen_re	logic
transition_regwen_qs	logic
transition_cmd_we	logic
transition_cmd_wd	logic
transition_ctrl_re	logic
transition_ctrl_we	logic
transition_ctrl_qs	logic
transition_ctrl_wd	logic
transition_token_0_re	logic
transition_token_0_we	logic
transition_token_0_qs	logic [31:0]
transition_token_0_wd	logic [31:0]
transition_token_1_re	logic
transition_token_1_we	logic
transition_token_1_qs	logic [31:0]
transition_token_1_wd	logic [31:0]
transition_token_2_re	logic
transition_token_2_we	logic
transition_token_2_qs	logic [31:0]
transition_token_2_wd	logic [31:0]
transition_token_3_re	logic
transition_token_3_we	logic
transition_token_3_qs	logic [31:0]
transition_token_3_wd	logic [31:0]
transition_target_re	logic
transition_target_we	logic
transition_target_qs	logic [4:0]
transition_target_wd	logic [4:0]
otp_vendor_test_ctrl_re	logic
otp_vendor_test_ctrl_we	logic
otp_vendor_test_ctrl_qs	logic [31:0]
otp_vendor_test_ctrl_wd	logic [31:0]
otp_vendor_test_status_re	logic
otp_vendor_test_status_qs	logic [31:0]
lc_state_re	logic
lc_state_qs	logic [4:0]
lc_transition_cnt_re	logic
lc_transition_cnt_qs	logic [4:0]
lc_id_state_re	logic
lc_id_state_qs	logic [1:0]
device_id_0_re	logic
device_id_0_qs	logic [31:0]
device_id_1_re	logic
device_id_1_qs	logic [31:0]
device_id_2_re	logic
device_id_2_qs	logic [31:0]
device_id_3_re	logic
device_id_3_qs	logic [31:0]
device_id_4_re	logic
device_id_4_qs	logic [31:0]
device_id_5_re	logic
device_id_5_qs	logic [31:0]
device_id_6_re	logic
device_id_6_qs	logic [31:0]
device_id_7_re	logic
device_id_7_qs	logic [31:0]
manuf_state_0_re	logic
manuf_state_0_qs	logic [31:0]
manuf_state_1_re	logic
manuf_state_1_qs	logic [31:0]
manuf_state_2_re	logic
manuf_state_2_qs	logic [31:0]
manuf_state_3_re	logic
manuf_state_3_qs	logic [31:0]
manuf_state_4_re	logic
manuf_state_4_qs	logic [31:0]
manuf_state_5_re	logic
manuf_state_5_qs	logic [31:0]
manuf_state_6_re	logic
manuf_state_6_qs	logic [31:0]
manuf_state_7_re	logic
manuf_state_7_qs	logic [31:0]
addr_hit	logic [31:0]
shadow_busy	logic	shadow busy
reg_busy_sel	logic	register busy
unused_wdata	logic	Unused signal tieoff wdata / byte enable are not always fully used add a blanket unused statement to handle lint waivers
unused_be	logic

Constants

Name	Type	Value	Description
AW	int	7
DW	int	32
DBW	int	DW/8	Byte Width

Processes

• unnamed: ( @(posedge clk_i or negedge rst_ni) )

• unnamed: ( )

• unnamed: ( )

• unnamed: ( )

• unnamed: ( )

Instantiations

• u_chk: tlul_cmd_intg_chk

• u_rsp_intg_gen: tlul_rsp_intg_gen

• u_reg_if: tlul_adapter_reg

• u_alert_test_fatal_prog_error: prim_subreg_ext

• u_alert_test_fatal_state_error: prim_subreg_ext

• u_alert_test_fatal_bus_integ_error: prim_subreg_ext

• u_status_ready: prim_subreg_ext

• u_status_transition_successful: prim_subreg_ext

• u_status_transition_count_error: prim_subreg_ext

• u_status_transition_error: prim_subreg_ext

• u_status_token_error: prim_subreg_ext

• u_status_flash_rma_error: prim_subreg_ext

• u_status_otp_error: prim_subreg_ext

• u_status_state_error: prim_subreg_ext

• u_status_bus_integ_error: prim_subreg_ext

• u_status_otp_partition_error: prim_subreg_ext

• u_claim_transition_if: prim_subreg_ext

• u_transition_regwen: prim_subreg_ext

• u_transition_cmd: prim_subreg_ext

• u_transition_ctrl: prim_subreg_ext

• u_transition_target: prim_subreg_ext

• u_otp_vendor_test_ctrl: prim_subreg_ext

• u_otp_vendor_test_status: prim_subreg_ext

• u_lc_state: prim_subreg_ext

• u_lc_transition_cnt: prim_subreg_ext

• u_lc_id_state: prim_subreg_ext